3

FN6947.0

December 15, 2009

Pin Configuration

ISL70001SRH

(48 LD CQFP)

TOP VIEW

7

8

9

10

11

12

13

14

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

15

16

17

18

19 20 21 22

39

40

41

42

43

44

45

46

47

48

1

2

3

4

5

6

PVIN3

LX3

PGND3

PGND3

PGND4

PGND4

LX4

PVIN4

PVIN4

PVIN5

PVIN5

LX5

M/S

ZAP

TDI

TDO

PGOOD

DVDD

DGND

DGND

AGND

AGND

SS

DVDD

Pin Descriptions

PIN NUMBER

PIN NAME

DESCRIPTION

1, 2, 27, 28, 29,

30, 37, 38, 39,

40, 47, 48

PGNDx

These pins are the power grounds associated with the corresponding internal power blocks.

Connect these pins directly to the ground plane. These pins should also connect to the

negative terminals of the input and output capacitors. Locate the input and output capacitors

as close as possible to the IC.

3, 26, 31, 36,

41, 46

LXx

These pins are the outputs of the corresponding internal power blocks and should be

connected to the output filter inductor. Internally, these pins are connected to the synchronous

MOSFET power switches. To minimize voltage undershoot, it is recommended that a Schottky

diode be connected from these pins to PGNDx. The Schottky diode should be located as close

as possible to the IC.

4, 5, 24, 25, 32,

33, 34, 35, 42,

43, 44, 45

PVINx

These pins are the power supply inputs to the corresponding internal power blocks. These pins

must be connected to a common power supply rail, which must fall in the range of 3V to 5.5V.

Bypass these pins directly to PGNDx with ceramic capacitors located as close as possible to

the IC.

6

SYNC

This pin is the synchronization I/O for the IC. When configured as an output (Master Mode),

this pin drives the SYNC input of another ISL70001SRH. When configured as an input (Slave

Mode), this pin accepts the SYNC output from another ISL70001SRH or an external clock.

Synchronization of the slave unit is 180° out-of-phase with respect to the master unit. If

synchronizing to an external clock, the clock must be SEE hardened and the frequency must

be within the range of 1MHz ±20%.

7

M/S

This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For

SYNC = Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode),

connect this pin to DGND.

8

ZAP

This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to

DGND.

9

TDI

This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.

10

TDO

This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.

ISL70001SRH