© Semiconductor Components Industries, LLC, 2009

August, 2009 − Rev. 0

1

Publication Order Number:

NB7VQ58M/D

NB7VQ58M

1.8V / 2.5V / 3.3V

Differential 2:1 Clock/Data

Multiplexer / Translator

with CML Outputs

w/ Selectable Input Equalizer

Multi−Level Inputs w/ Internal Termination

Description

The NB7VQ58M is a high performance differential 2−to−1 Clock or

Data multiplexer with a selectable Equalizer receiver. When placed in

series with a Clock /Data path operating up to 7 GHz or 10.7 Gb/s,

respectively, the NB7VQ58M inputs will compensate the degraded

signal transmitted across an FR4 PCB backplane or cable

interconnect. Therefore, the serial data rate is increased by reducing

Inter−Symbol Interference (ISI) caused by losses in copper

interconnect or long cables.

The EQualizer ENable pin (EQEN) allows the INn/INn inputs to

either flow through or bypass the Equalizer section. Control of the

Equalizer function is realized by setting EQEN; When EQEN is set

Low, the INn / INn inputs bypass the Equalizer. When EQEN is set

High, the INn / INn inputs flow through the Equalizer. The default

state at startup is LOW. As such, the NB7VQ58M is ideal for SONET,

GigE, Fiber Channel, Backplane and other Clock/Data distribution

applications.

The differential inputs incorporate internal 50

W termination

resistors that are accessed through the VT pin. This feature allows the

NB7VQ58M to accept various logic level standards, such as LVPECL,

CML or LVDS.

The NB7VQ58M produces minimal Clock or Data jitter operating

up to 7 GHz or 10.7 Gb/s, respectively.

The 16 mA differential CML outputs provide matching internal

50

W terminations and 400 mV output swings when externally

terminated with a 50

The NB7VQ58M is offered in a low profile 3mm x 3 mm 16−pin

QFN package and is a member of the GigaComm

™ family of high

performance Clock / Data products. Application notes, models, and

support documentation are available at www.onsemi.com.

Features

Typical

0 V

A

= Assembly Location

L

= Wafer Lot

Y

= Year

W

= Work Week

G

= Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

MARKING

DIAGRAM*

QFN−16

MN SUFFIX

CASE 485G

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

ORDERING INFORMATION

16

NB7V

Q58M

ALYW G

G

1

SIMPLIFIED BLOCK DIAGRAM

(Note: Microdot may be in either location)

1

EQ