NCP5386A datasheet(10/33 Pages) ONSEMI

Part #	NCP5386A

Description	1/2 Phase Controller for CPU and Chipset Applications

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Manufacturer	ONSEMI [ON Semiconductor]

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NCP5386, NCP5386A, NCP5386B

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10

ELECTRICAL CHARACTERISTICS

(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF)

Parameter

Units

Max

Typ

Min

Test Conditions

PWM Outputs

Output Low Voltage

Sinking 500 mA

−

0.15

V

Rise Time

CL = 20 pF, DVO = 0.3 to 2.0 V

−

20

ns

Fall Time

CL = 20 pF, DVO = Vmax to 0.7 V

−

20

ns

Tri−State Output Leakage

Gx = 2.5 V, x = 1 − 4

−

1.5

mA

Output Impedance − Sourcing

Maximum Resistance to VCC

−

320

−

W

Output Impedance − Sinking

Maximum Resistance to GND

−

140

−

W

DRVON

Output High Voltage

Sourcing 500 mA

3.0

−

VCC

V

Output Low Voltage

Sinking 500 mA

−

0.7

mV

Rise Time

CL (PCB) = 20 pF, DVO = 10% to 90%

−

24

30

ns

Fall Time

CL = 20 pF, DVO = 10% to 90%

−

11

20

ns

Internal Pulldown Resistance

−

70

−

kW

Soft−Start

Soft−Start Pin Source Current

3.75

5.0

6.25

mA

Soft−Start Ramp Time

CSS = 0.01 mF; Time to 1.05 V

−

2.2

−

ms

Soft−Start Pin Discharge Voltage

DRVON pin = LO (Fault)

−

25

mV

VR11 Dwell Time at VBOOT

CSS = 0.01 mF

50

−

500

ms

DACMODE Input

Input Range for AMD Operating Mode

2.3

−

3.5

V

Input Range for VR11 Operating Mode

0.9

−

1.7

V

Input Range for VR10 Operating Mode

0

−

0.5

V

Enable Input

Enable High Input Leakage Current

EN = 3.3 V

−

1.0

mA

Rising Threshold

VUPPER

0.800

−

0.920

V

Falling Threshold

VLOWER

0.670

−

0.830

V

Hysteresis

VUPPER – VLOWER

−

130

−

mV

Enable Delay Time

Time from Enable transitioning HI to initiation

of Soft−Start

1.0

−

5.0

ms

Disable Delay Time

EN Low to DRVON Low

−

150

200

ns

Current Limit

Current Sense Amp to ILIM Gain

20 mV < (CSx − CSxN) < 60 mV

(Each CS Input Independently)

5.7

5.95

6.2

V/V

ILIM Pin Input Bias Current

VILIM = 2.0 V

−

1.0

mA

ILIM Pin Working Voltage Range

0.2

−

2.0

V

ILIM Offset Voltage

Offset extrapolated to CSx − CSxN = 0,

referred to ILIM pin

−33

17

67

mV

Delay (Note 3)

−

300

−

ns

3. Guaranteed by design. Not tested in production.

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