PRELIMINARY
PSoC®5: CY8C52 Family Data Sheet
Document Number: 001-55034 Rev. *A
Page 9 of 85
Figure 2-5. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance
3. Pin Descriptions
Extref0, Extref1.
External reference input to the analog system.
GPIO.
General purpose I/O pin provides interfaces to the CPU,
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense®[4].
I2C0: SCL, I2C1: SCL.
I2C SCL line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SCL if
wake from sleep is not required.
I2C0: SDA, I2C1: SDA.
I2C SDA line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SDA if
wake from sleep is not required.
Ind.
Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi.
32.768 kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi.
4 to 33 MHz crystal oscillator
pin.
nTRST.
Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
SIO.
Special I/O provides interfaces to the CPU, digital periph-
erals and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
SWDCK.
Serial Wire Debug Clock programming and debug port
connection.
SWDIO.
Serial Wire Debug Input and Output programming and
debug port connection.
TCK.
JTAG Test Clock programming and debug port connection.
TDI.
JTAG
Test
Data
In
programming
and
debug
port
connection.
TDO.
JTAG Test Data Out programming and debug port
connection.
TMS.
JTAG Test Mode Select programming and debug port
connection.
TRACECLK.
Cortex-M3
TRACEPORT
connection,
clocks
TRACEDATA pins.
TRACEDATA[3:0].
Cortex-M3
TRACEPORT
connections,
output data.
SWV.
Single Wire Viewer output.
USBIO, D+.
Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from Vddd instead
of from a Vddio. Pins are No Connect (NC) on devices without
USB.[2]
USBIO, D-.
Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from Vddd instead
of from a Vddio. Pins are No Connect (NC) on devices without
USB.[2]
Vboost.
Power sense connection to boost pump.
Vbat.
Battery supply to boost pump.
Vcca.
Output of analog core regulator and input to analog core.
Requires a 1 µF capacitor to Vssa. Regulator output not for
external use.
Vccd.
Output of digital core regulator and input to digital core.
Requires a capacitor from each Vccd pin to Vssd; see Power
System on page 22. Regulator output not for external use.
Vdda.
Supply for all analog peripherals and analog core
regulator. Vdda must be the highest voltage present on the
device. All other supply pins must be less than or equal to
Vdda.
VDDD
VSSD
VDDA
VSSA
VSSD
Plane
VSSA
Plane
Note
4. GPIOs with OpAmp outputs are not recommended for use with CapSense.
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