PRELIMINARY
PSoC®5: CY8C52 Family Data Sheet
Document Number: 001-55034 Rev. *A
Page 4 of 85
Figure 1-1 illustrates the major components of the CY8C52
family. They are:
ARM Cortex-M3 CPU Subsystem
Nonvolatile Subsystem
Programming, Debug, and Test Subsystem
Inputs and Outputs
Clocking
Power
Digital Subsystem
Analog Subsystem
PSoC’s digital subsystem provides half of its unique config-
urability. It connects a digital signal from any peripheral to any
pin through the Digital System Interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power Universal Digital Blocks (UDBs). PSoC Creator provides
a library of pre-built and tested standard digital peripherals
(UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR,
and so on) that are mapped to the UDB array. The designer can
also easily create a digital circuit using boolean primitives by
means of graphical design entry. Each UDB contains Program-
mable Array Logic (PAL)/Programmable Logic Device (PLD)
functionality, together with a small state machine engine to
support a wide variety of peripherals.
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C52 family these blocks can include four 16-bit timer,
counter, and PWM blocks; I2C slave, master, and multi-master;
Full-Speed USB; and Full CAN 2.0b.
For more details on the peripherals see the “Example Periph-
erals” section on page 33 of this data sheet. For information on
UDBs, DSI, and other digital blocks, see the “Digital Subsystem”
section on page 32 of this data sheet.
PSoC’s analog subsystem is the second half of its unique config-
urability. All analog performance is based on a highly accurate
absolute voltage reference with less than 0.1% error over
temperature and voltage. The configurable analog subsystem
includes:
Analog muxes
Comparators
Analog mixers
Voltage references
Analog-to-Digital Converter (ADC)
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
The CY8C52 family offers a Successive Approximation Register
(SAR) ADC. Featuring 12-bit conversions at up to 1M samples
per second, it also offers low nonlinearity and offset errors and
SNR better than 70 dB. It is well suited for a variety of higher
speed analog applications.
In addition to the ADC, the analog subsystem provides multiple
comparators.
See the “Analog Subsystem” section on page 45 of this data
sheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 40 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, Flash
cache, and RAM. The NVIC provides low latency, nested inter-
rupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The Flash cache also reduces system power consumption by
allowing less frequent Flash access.
PSoC’s nonvolatile subsystem consists of Flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 256 KB of on-chip Flash. The CPU can reprogram individual
blocks of Flash, enabling boot loaders. The designer can enable
an Error Correcting Code (ECC) for high reliability applications.
A powerful and flexible protection model secures the user's
sensitive information, allowing selective memory block locking
for read and write protection. Two KB of byte-writable EEPROM
is available on-chip to store application data. Additionally,
selected configuration options such as boot speed and pin drive
mode are stored in nonvolatile memory. This allows settings to
activate immediately after power on reset (POR).
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the Vddio pins. Every GPIO
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow Voh
to be set independently of Vddio when used as outputs. When
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I2C bus where the PSoC may not be powered when
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
make the SIO function as a general purpose analog comparator.
For devices with Full-Speed USB the USB physical interface is
also provided (USBIO). When not using USB these pins may
also be used for limited digital functionality and device
programming. All the features of the PSoC I/Os are covered in
detail in the “I/O System and Routing” section on page 26 of this
data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability, and factory trimmed for absolute
accuracy. The Internal Main Oscillator (IMO) is the master clock
base for the system with 1% absolute accuracy at 3 MHz. The
IMO can be configured to run from 3 MHz up to 72 MHz. Multiple
clock derivatives can be generated from the main clock
frequency to meet application needs. The device provides a PLL
to generate system clock frequencies up to 39 MHz (40 MHz
including +1% tolerance) from the IMO, external crystal, or
external reference clock. It also contains a separate, very low
power Internal Low Speed Oscillator (ILO) for the sleep and
watchdog timers. A 32.768 kHz external watch crystal is also
supported for use in Real Time Clock (RTC) applications. The
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