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LM5033 Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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LM5033 Datasheet(HTML) 9 Page - National Semiconductor (TI) |
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9 / 17 page  Current Sense (Pin 8) (Continued) The external current sensing circuit should include an RC filter located near the IC to prevent false triggering of the Current Sense comparator due to transients or noise. An internal MOSFET discharges the external filter capacitor at the conclusion of each PWM cycle to improve dynamic performance. The discharge time is equal to the deadtime between Out1 and Out2 at maximum duty cycle. Additionally, pin 8 is pulled low when V CC is below the under-voltage threshold or when an over temperature condition occurs. Oscillator, Sync Capability (Pin 9) The LM5033 oscillator frequency is set by a single external resistor connected between Rt/Sync and ground. The re- quired Rt resistor is calculated from: The outputs (Out1 and Out2) alternate at half the oscillator frequency. The voltage at the Rt/Sync pin is internally regu- lated to a nominal 2.0V. The Rt resistor should be located as close as possible to the IC, and connected directly to the pins (Rt and GND). The LM5033 can be synchronized to an external clock by applying a narrow pulse to pin 9. The external clock must be a higher frequency than the free running frequency set by the Rt resistor, and the pulse width must be between 15 and 150 ns. The clock signal must be coupled into the Rt/Sync pin through a 100 pF capacitor. When the synchronizing pulse transitions low-to-high, the voltage at pin 9 must ex- ceed 3.8V from its nominal 2.0V dc level. During the clock signal’s low time the voltage at pin 9 will be clamped at 2.0V by an internal regulator. The Rt resistor is always required, whether the oscillator is free running or externally synchro- nized. Soft Start (Pin 10) The softstart feature allows the converter to gradually reach a steady state operating point, thereby reducing start-up stresses and current surges. Upon turn-on, after the under- voltage sensor resets at V CC, an internal 10 µA current source charges an external capacitor at pin 10 to generate a ramping voltage (0 to + 5V) which allows the voltage on the Comp pin (pin 3) to increase gradually. As the COMP voltage increases the output duty cycle will increase from zero to the value required for regulation. Internally, the softstart pin is pulled low when a current fault is detected at pin 8, the V CC voltage is below the lower threshold of the under-voltage sensor, or when a thermal shutdown occurs. Additionally, the softstart pin can be pulled low by an external device. In the event of a current fault, (see Current Sense section) the softstart capacitor will be discharged by an internal pull- down device. The falling voltage at pin 10 will pull down the COMP pin, thereby ensuring a minimum output duty cycle when the outputs are re-enabled. The softstart capacitor will then begin to ramp up, allowing the COMP voltage to in- crease. As the COMP voltage increases, the output duty cycle increases from zero to the value required for regula- tion. However, if the fault condition is still present the above sequence repeats until the fault is removed. If the V CC voltage falls below the lower under-voltage sensor threshold (typically 6.8V) the outputs are disabled, and the softstart capacitor is discharged. The falling voltage at pin 10 will pull down the COMP pin, thereby ensuring minimum output duty cycle when the outputs are re-enabled. After the V CC voltage increases above the upper threshold (typically 9.5V), the outputs are enabled, and the softstart capacitor will begin to ramp up, allowing the COMP pin voltage to increase. The output duty cycle will then increase from zero to the value required for regulation. In the event of a fault which results in an excessively high die temperature, an internal Thermal Shutdown circuit is pro- vided to protect the IC. When activated (at 165˚C) the IC is forced into a low power reset state, disabling the output drivers and the V CC regulator. When the die temperature has reduced (typical hysteresis = 15˚C), the V CC regulator is enabled and a softstart sequence will initiate. Using an externally controlled switch, the outputs (Pins 5 & 6) can be disabled at any time by pulling pin 10 below 0.5V. This will pull down the COMP pin to near ground, causing the output duty cycle to go to zero. Upon releasing pin 10, the softstart capacitor will ramp up, allowing the COMP pin voltage to increase. The output duty cycle then increases from zero to the value required for regulation. OUT1, OUT2 (Pins 5, 6) The LM5033 provides two alternating outputs, OUT1 and OUT2, each capable of sourcing and sinking 1.5A peak. Each will toggle at one-half the internal oscillator frequency. The voltage output levels are nominally ground and V CC, minus a saturation voltage at each level which depends on the current flow. The outputs can drive power MOSFETs directly in a push- pull application, or they can drive a high voltage gate driver (e.g., LM5100) in a bridge application. The outputs are disabled when any of the following condi- tions occur: 1. An overcurrent condition is detected at pin 8, 2. The V CC under-voltage sensor is active, 3. An over-temperature condition is detected, or 4. The voltage at Pin 10 is below 0.5V Thermal Protection The system design should limit the LM5033 junction tem- perature to not exceed 125˚C during normal operation. How- ever, in the event of a fault which results in a higher die temperature, an internal Thermal Shutdown circuit is pro- vided to protect the IC. When thermal shutdown is activated, typically at 165˚C, the IC is forced into a low power reset state disabling the output drivers and the V CC regulator. This feature helps prevent catastrophic failures from accidental device overheating. When the die temperature has reduced (typical hysteresis = 15˚C) the V CC regulator is enabled and a softstart sequence initiates. Application Information The following information is intended to provide guidelines for implementing the LM5033. However, final selection of all external components is dependent on the configuration and operating characteristics of the complete power conversion system. www.national.com 9 |
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Similar Description - LM5033_05 |
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