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DAC3282IRGZT Datasheet(PDF) 4 Page - Texas Instruments |
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DAC3282IRGZT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 49 page DAC3282 SLAS646 – DECEMBER 2009 www.ti.com PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. DACCLKP 3 I Positive external LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2. DACCLKN 4 I Complementary external LVPECL clock input for DAC core. (see the DACCLKP description) DAC core supply voltage. (1.8 V) DACVDD18 2, 35 I It is recommended to isolate this supply from CLKVDD18 and DIGVDD18. LVDS positive input data clock. This positive/negative pair has an internal 100 Ω termination resistor. DATACLKP 17 I Input data D[7:0]P/N is latched on both edges of DATACLKP/N (Double Data Rate) with two data transfers input per DATACLKP/N clock cycle. DATACLKN 18 I LVDS negative input data clock. (See DATACLKP description) Digital supply voltage. (1.8V) DIGVDD18 8, 29 I It is recommended to isolate this supply from CLKVDD18 and DACVDD18. Used as external reference input when internal reference is disabled through CONFIG25 extref_ena = EXTIO 44 I/O ‘1’. Used as internal reference output when CONFIG25 extref_ena = ‘0’ (default). Requires a 0.1 μF decoupling capacitor to AGND when used as reference output. LVDS frame indicator positive input. This positive/negative pair has an internal 100 Ω termination resistor. This signal is captured with the rising edge of DATACLKP/N and used to indicate the FRAMEP 19 I beginning of the frame. It is also used as a reset signal by the FIFO. The FRAMEP/N signal should be edge-aligned with D[7:0]P/N. FRAMEN 20 I LVDS frame indicator negative input. (See the FRAMEN description) LVPECL FIFO output strobe positive input. Similar to FIFO_ISTR but it is captured with the rising edge FIFO_OSTRP 6 I of DACCLKP/N. It is used to reset the clock dividers as well as the FIFO read pointer. If unused it can be left floating. FIFO_OSTRN 7 I LVPECL FIFO output strobe negative input. (See the FIFO_OSTRP description) 5, Thermal GND I Pin 5 and the Thermal Pad located on the bottom of the QFN package is ground for all supplies. Pad A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a IOUTA1 38 O full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin. A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1 IOUTA2 39 O described above. An input data value of 0x0000 results in a 0 mA sink and the most positive voltage on the IOUTA2 pin. IOUTB1 47 O B-Channel DAC current output. Refer to IOUTA1 description above. IOUTB2 46 O B-Channel DAC complementary current output. Refer to IOUTA2 description above. LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of OSTRP 6 I DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can be left floating. OSTRN 7 I LVPECL output strobe negative input. (See the OSTRP description) RESETB 36 I 1.8V CMOS active low input for chip RESET. Internal pull-up. SCLK 32 I 1.8V CMOS serial interface clock. Internal pull-down. SDENB 33 I 1.8V CMOS active low serial data enable, always an input to the DAC3282. Internal pull-up. 1.8V CMOS serial interface data. Bi-directional in 3-pin mode (default). In 4-pin interface mode, the SDIO 31 I/O SDIO pin is an input only. Internal pull-down. 1.8V CMOS active high input. TXENABLE must be high for the DATA to the DAC to be enabled. TXENABLE 30 I When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal pull-down. Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to VFUSE 41 I DACVDD18 pins for normal operation. 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC3282 |
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