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DRV8412 Datasheet(PDF) 3 Page - Texas Instruments |
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DRV8412 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 28 page  DRV8412 DRV8422 DRV8432 www.ti.com SLES242A – DECEMBER 2009 – REVISED DECEMBER 2009 PACKAGE HEAT DISSIPATION RATINGS PARAMETER DRV8412 DRV8422 DRV8432 RθJC, junction-to-case (power pad / heat 1.1 °C/W 1.1 °C/W 0.9 °C/W slug) thermal resistance This device is not intended to This device is not intended to be used without a heatsink. be used without a heatsink. RθJA, junction-to-ambient thermal 25 °C/W Therefore, RθJA is not Therefore, RθJA is not resistance specified. See the Thermal specified. See the Thermal Information section. Information section. Exposed power pad / heat slug area 34 mm2 34 mm2 80 mm2 PACKAGE POWER DERATINGS (DRV8412) (1) DERATING TA = 25°C POWER PACKAGE FACTOR ABOVE TA = 70°C POWER RATING TA = 85°C POWER RATING RATING TA = 25°C 44-PIN TSSOP (DDW) 5.0 W 40.0 mW/°C 3.2 W 2.6 W (1) Based on EVM board layout MODE SELECTION PINS MODE PINS OUTPUT DESCRIPTION CONFIGURATION M3 M2 M1 Dual full bridges (two PWM inputs each full bridge) or four half bridges with 0 0 0 2 FB or 4 HB cycle-by-cycle current limit Dual full bridges (two PWM inputs each full bridge) or four half bridges with 0 0 1 2 FB or 4 HB OC latching shutdown (no cycle-by-cycle current limit) 0 1 0 1 PFB Parallel full bridge with cycle-by-cycle current limit Dual full bridges (one PWM input each full bridge with complementary PWM 0 1 1 2 FB on second half bridge) with cycle-by-cycle current limit 1 x x Reserved Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): DRV8412 DRV8422 DRV8432 |
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