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TAS5713PHP Datasheet(PDF) 9 Page - Texas Instruments |
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TAS5713PHP Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 63 page  TAS5713 www.ti.com SLOS637 – DECEMBER 2009 PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fMCLKI MCLK frequency 2.8224 24.576 MHz MCLK duty cycle 40% 50% 60% tr / Rise/fall time for MCLK 5 ns tf(MCLK) LRCLK allowable drift before LRCLK reset 4 MCLKs External PLL filter capacitor C1 SMD 0603 X7R 47 nF External PLL filter capacitor C2 SMD 0603 X7R 4.7 nF External PLL filter resistor R SMD 0603, metal film 470 Ω ELECTRICAL CHARACTERISTICS DC Characteristics TA = 25°, PVCC_x = 18 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL AD mode, fS = 48 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH = –4 mA VOH High-level output voltage A_SEL_FAULT and SDA 2.4 V DVDD = 3 V IOL = 4 mA VOL Low-level output voltage A_SEL_FAULT and SDA 0.5 V DVDD = 3 V VI < VIL ; DVDD = AVDD IIL Low-level input current 75 μA = 3.6V VI > VIH ; DVDD = IIH High-level input current 75(1) μA AVDD = 3.6V Normal mode 48 83 3.3 V supply voltage (DVDD, IDD 3.3 V supply current mA Reset (RESET = low, 26 40 AVDD) PDN = high) Normal mode 41 75 IPVDD Supply current No load (PVDD_x) mA Reset (RESET = low, 5 13 PDN = high) Drain-to-source resistance, LS TJ = 25°C, includes metallization resistance 110 rDS(on) (2) m Ω Drain-to-source resistance, TJ = 25°C, includes metallization resistance 110 HS I/O Protection Vuvp Undervoltage protection limit PVDD falling 7.2 V Vuvp,hyst Undervoltage protection limit PVDD rising 7.6 V OTE(3) Overtemperature error 150 °C Extra temperature drop OTEHYST (3) 30 °C required to recover from error OLPC Overload protection counter fPWM = 384 kHz 0.63 ms IOC Overcurrent limit protection 4.5 A IOCT Overcurrent response time 150 ns Internal pulldown resistor at Connected when drivers are tristated to provide bootstrap RPD 3 k Ω the output of each half-bridge capacitor charge. (1) IIH for the PBTL pin has a maximum limit of 200 µA due to an internal pulldown on the pin. (2) This does not include bond-wire or pin resistance. (3) Specified by design Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TAS5713 |
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