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TPS658600 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS658600 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 105 page  TPS658600 www.ti.com SLVSA37 – DECEMBER 2009 2.4 ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT QUIESCENT CURRENT – V(BAT) = 4.2V NO EXTERNAL LOADS AT SYS PIN OR SUPPLY OUTPUTS Quiescent current, 6586x in normal or sleep IQ(ON) Power path active, control logic in low power mode (1) 375 μA mode. All supplies, peripherals and charger off IQ(DIGITAL) Quiescent current, control logic Control logic in high power mode (2) 584 716 870 μA SM0, SM1: enabled, PFM mode, from SYS pin 14 25 μA SM2: enabled, PFM mode, from SYS pin 19 32 μA IQ(SMn) SM0, SM1, SM2 operating quiescent current SM0, SM1, SM2: enabled, PWM mode, from VINSMn pin 6 mA 1 μA disabled via I 2C I(LDOx) = no external load 24 29 μA I(LDOx) = –1 mA 24 150 μA LDO quiescent current, All but one LDOx IQ(LDOx) disabled I(LDOx) = –50 mA 160 μA LDO disabled, TJ = 85°C 1 3 μA SM3 enabled, not switching 15 30 μA Enabled, switching 200 μA IQ(SM3) SM3 operating quiescent current (3) 1 μA Disabled via I 2C Conversion active 1 mA Not converting, waiting for trigger 170 μA IQ(ADC) ADC operating quiescent current 1 μA ADC disabled via I 2C RTC_OUT LDO enabled 27 45 μA RTC_OUT disabled via I 2C, T J = 85°C . Externally applied (4) IQ(RTC) RTC_OUT pin quiescent current 15 μA V(RTC_OUT) = 2 V supplies real time clock counters and xtal oscillator 32k buffer enabled, 100 pF external load 24 μA IQ(V32K) V32K supply bias current , 32k buffer enabled 8 μA Disabled via I 2C Charger enabled, termination detected 40 50 μA IQ(CHG) Charger quiescent current Charger enabled, termination disabled, charge current=0 (3) 2 mA Charger disabled 10 20 μA I 2C INTERFACE TIMING – SDA, PSDA, PSCLK, SCLK(3) TR SCLK/SDATA rise time 300 ns TF SCLK/SDATA fall time 300 ns TW(H) SCLK pulse width high 600 ns TW(L) SCLK Pulse Width Low 1.3 μs TSU(STA) Setup time for START condition 600 ns TH(STA) START condition hold time after which first clock 600 ns pulse is generated Pull-up resistors connected to 2.2V TSU(DAT) Data setup time 100 ns TH(DAT) Data hold time 0 ns TSU(STOP) Setup time for STOP condition 600 ns Bus free time between START and STOP T(BUF) 1.3 μs condition FSCL Clock Frequency 400 kHz I 2C BUFFERS – SDA, PSDA, PSCLK, SCLK VIL(I2C) Low level input voltage 0.4 V VIH(I2C) High level input voltage 1.15 V VOL(I2C) Low level output voltage SDA, PSDA configured as output, IOL=3mA 0.4 V IO(I2C) Maximum load current (3) SDA, PSDA configured as output 8 mA ILKG(I2C) Input current V(pin)=5V or 0V 1.0 μA CI2C Input pin capacitance SDAT, SCLK, PSDAT, PSCLK pins 10 pF CI2CBUS SDAT, SCLK, PSDAT, PSCLK 400 pF I 2C bus capacitance (1) Control logic in low power mode when all functions are off and no I2C communication is on going (2) Control logic in high power mode when one of the following events happen: 6586x in power-up/rtc/rtc_on/supplyseq states, any converter in PWM mode, SM3 enabled, PWM driver enabled, ADC conversion on-going, I2C communication on-going, voltage transition for DVM supplies on-going, charger on, AC or USB supply detected, initial power-up cycle. (3) Not production tested. (4) External voltage supplied by supercap or coin cell connected to RTC_OUT pin, see application diagram for details. Copyright © 2009, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 5 Submit Documentation Feedback Product Folder Link(s): TPS658600 |
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