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ADE7858ACPZ-REF Datasheet(PDF) 8 Page - Analog Devices |
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ADE7858ACPZ-REF Datasheet(HTML) 8 Page - Analog Devices |
8 / 76 page ADE7858 Preliminary Technical Data Rev. PrA| Page 8 of 76 Table 3. SPI INTERFACE TIMING Parameter Parameter Symbol Min Max Unit SS to SCLK edge tSS 50 ns SCLK period 400 ns SCLK low pulse width tSL 175 ns SCLK high pulse width tSH 175 ns Data output valid after SCLK edge tDAV 5 40 ns Data input setup time before SCLK edge tDSU 20 ns Data input hold time after SCLK edge tDHD 5 ns Data output fall time tDF 20 ns Data output rise time tDR 20 ns SCLK rise time tSR 20 ns SCLK fall time tSF 20 ns MISO disable after SS rising edge tDIS 5 40 ns SS high after SCLK edge tSFS 0 ns SS SCLK MISO MOSI t SS t SL t DSU t SH t DHD t DF t DR t SR t SF t SFS t DIS MSB INTERMEDIATE BITS LSB MSB IN INTERMEDIATE BITS LSB IN t DAV Figure 3. SPI Interface Timing |
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