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71M6511-IGTR Datasheet(PDF) 9 Page - Teridian Semiconductor Corporation |
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71M6511-IGTR Datasheet(HTML) 9 Page - Teridian Semiconductor Corporation |
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9 / 95 page  71M6511/71M6511H Single-Phase Energy Meter IC DATA SHEET AUGUST 2007 Page: 9 of 95 © 2005-2007 TERIDIAN Semiconductor Corporation V2.6 The Multiplexer Control Circuit handles the setting of the multiplexer. The function of the Multiplexer Control Circuit is governed by the I/O RAM registers MUX_ALT (0x2005[2]), EQU (0x2000[7:5]), and MUX_DIV (0x2002[7:6]). MUX_DIV controls the number of samples per cycle. It can request 2, 3, 4, or 6 multiplexer states per cycle. The MUX_ALT bit requests an alternate multiplexer cycle. The bit may be asserted on any MPU cycle and may be sub- sequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT will cause the Control Circuit to wait until the next multiplexer cycle and implement a single alternate cycle. Multiplexer Control Circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage, VREF. The Multiplexer Control Circuit is clocked by CK32, the 32768Hz clock from the PLL block, and launches each pass through the CE program. Table 2 shows the possible settings for MUX_DIV and FIR_LEN and the resulting channels sampled along with sample frequencies. Number of CK32 states for code pass Effective sample frequency [Hz] Number of CK32 states for code pass Effective sample frequency [Hz] MUX_DIV (0x2002[7.6]) Number of channels selected (mux states per cycle) FIR_LEN = 0 FIR_LEN =1 00 --- Not Allowed 01 4 9 3640.89 13 2520.615 10 3 7 4681.143 10 3276.8 11 2 5 6553.6 7 4681.143 Table 2: Channel control based on MUX_DIV and FIR_LEN ADC A single 21/22-bit delta-sigma A/D converter (ADC) digitizes the power inputs to the AFE. The resolution of the ADC is programmable using the I/O RAM register FIR_LEN register (0x2005[4]). ADC resolution may be selected to be 21 bits (FIR_LEN=0), or 22 bits (FIR_LEN=1). Conversion time is two cycles of CK32 with FIR_LEN = 0 and three cycles with FIR_LEN = 1. In order to provide the maximum resolution, the ADC should be operated with FIR_LEN = 1. Accuracy, timing and functional specifications in this data sheet are based on FIR_LEN = 1 and MUX_DIV = 1 (four CK32 cycles). Alternative specifications are also provided for FIR_LEN = 1 and MUX_DIV = 2 (three CK32 cycles) in the CE Program and Environment section. Initiation of each ADC conversion is controlled by the Multiplexer Control Circuit as described previously. FIR Filter The finite impulse response (FIR) filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose of the FIR is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output data of the FIR filter (raw data) is stored into the CE DRAM location determined by the multiplexer selection. The location of the raw data in the CE DRAM is specified in the CE Program and Environment Section. Voltage Reference The 71M6511/6511H includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference of the 71M6511H is trimmed in production to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coefficient. |
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