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73M1903C Datasheet(PDF) 4 Page - Teridian Semiconductor Corporation |
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73M1903C Datasheet(HTML) 4 Page - Teridian Semiconductor Corporation |
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4 / 46 page  73M1903C Modem Analog Front End DATA SHEET Page: 4 of 46 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 4.3 PIN DESCRIPTION The TERIDIAN 73M1903C modem Analog Front End (AFE) IC is available in a 32 pin QFN package. The following table describes the function of each pin. There are three pairs of power supply pins, VPA (analog), VPD (digital) and VPPLL (PLL). They should be separately decoupled from the supply source in order to isolate digital noise from the analog circuits internal to the chip. VPPLL can be directly connected to VPD. Failure to adequately isolate and decouple these supplies will compromise device performance. PIN NAME TYPE PIN # DESCRIPTION VND GND 1, 22 Negative Digital Ground VNA GND 16 Negative Analog Ground VPD PWR 2, 25 Positive Digital Supply VPA PWR 9 Positive Analog Supply VPPLL PWR 20 Positive PLL Supply, shared with VPD VNPLL PWR 17 Negative PLL Ground RST I 26 Master reset. When this pin is a logic 0 all registers are reset to their default states; Weak-pulled high-default. A low pulse longer than 100ns is needed to reset the device. The device will be ready within 100us after this pin goes to logic 1 state. OSCIN I 19 Crystal oscillator input. When providing an external clock source, drive OSCIN. OSCOUT O 18 Crystal oscillator circuit output pin. GPIO(0-7) I/O 3, 4, 5, 6, 23 24, 30, 31 Software definable digital input/output pins. RXAN I 14 Receive analog negative input. RXAP I 15 Receive analog positive input. TXAN1 O 10 Transmit analog negative output 1 TXAN2 O 11 Transmit analog negative output 2 TXAP1 O 12 Transmit analog positive output 1 TXAP2 O 13 Transmit analog positive output 2 SCLK I/O 8 Serial interface clock. With master mode and SCLK continuous selected, Freq = 256*Fs ( =2.4576MHz for Fs=9.6kHz). For slave mode, this pin must be pulled down by a resistor (<4.7kΩ). SDOUT O 32 Serial data output (or input to the host). SDIN I 29 Serial data input (or output from the host) FS O 7 Frame synchronization. (Active Low) TYPE I 27 Type of frame sync. 0 = late (mode0); 1 = early (mode1). Weak-pulled high – default SckMode I 28 Controls the SCLK behavior after FS. Open, weak-pulled high = SCLK Continuous; tied low = 32 clocks per R/W cycle. FSD O 21 Delayed frame sync to support daisy chain mode with additional 73M1903C devices Table 1: 32 QFN Pin Description |
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