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78P2351R Datasheet(PDF) 9 Page - Teridian Semiconductor Corporation |
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78P2351R Datasheet(HTML) 9 Page - Teridian Semiconductor Corporation |
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9 / 31 page  78P2351R Serial 155M NRZ to CMI Converter Page: 9 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 REGISTER DESCRIPTION (continued) LEGEND TYPE DESCRIPTION TYPE DESCRIPTION R/O Read only R/W Read or Write R/C Read and Clear GLOBAL REGISTERS ADDRESS 0-0: MASTER CONTROL REGISTER BIT NAME TYPE DFLT VALUE DESCRIPTION 7:5 -- R/W 0X0 Reserved. 4:3 CKSL [1:0] R/W X Reference Clock Frequency Select: Selects the reference clock frequency input at CKREFP/N pins. 11: 155.52 MHz (differential LVPECL input) 10: 77.76 MHz (single-ended CMOS input) – Tie CKREFN to ground. 00: 19.44 MHz (single-ended CMOS input) – Tie CKREFN to ground. Note: Default values depend on the CKSL pin setting upon reset or power up. 2:1 -- R/W X0 Reserved. 0 SRST R/W 0 Register Soft-Reset: When this bit is set, all registers are reset to their default values. This register bit is self-clearing. ADDRESS 0-1: RESERVED BIT NAME TYPE DFLT VALUE DESCRIPTION 7:0 -- R/W 00100X11 Reserved. ADDRESS 0-2: RESERVED BIT NAME TYPE DFLT VALUE DESCRIPTION 7:0 -- R/W XXXXXXX0 Reserved. |
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