Electronic Components Datasheet Search |
|
PEX8618-BA50BCG Datasheet(PDF) 1 Page - PLX Technology |
|
PEX8618-BA50BCG Datasheet(HTML) 1 Page - PLX Technology |
1 / 4 page Flexible & Versatile 16-lane 16-port PCI Express ® Switch Features PEX 8618 General Features o 16-lane PCI Express switch - Integrated 5.0 GT/s SerDes o Up to 16 configurable ports o 19 x 19mm 2, 324-ball HSBGA o Typical Power: 1.93 Watts PEX 8618 Key Features o Standards Compliant - PCI Express Base Specification r2.0 (Backwards compatible with PCIe r1.0a/1.1) - PCI Power Management Spec r1.2 - Microsoft Vista Compliant - Supports Access Control Services - Dynamic link-width control o High Performance - Non-blocking internal architecture - Full line rate on all ports - Cut-Thru latency: 140ns - 2KB max payload size - Read Pacing (intelligent bandwidth allocation) - Dual Cast o Dual-Host & Fail-Over Support - Configurable Non-Transparent port (NTB) - Moveable upstream port - Crosslink port capability o Flexible Configuration - 16 flexible & configurable ports (x1, x4, or x8) - Configurable with strapping pins, EEPROM, I 2C, or Host software - Lane and polarity reversal o PCI Express Power Management - Link power management states: L0, L0s, L1, L2/L3 Ready, and L3 - Device states: D0 and D3hot o Spread Spectrum Clock Isolation - Dual clock domain o Quality of Service (QoS) - Two Virtual Channels (VC) per port - Eight Traffic Classes per port - Weighted Round-Robin Port & VC Arbitration o Reliability, Availability, Serviceability - All ports Hot-Plug capable thru I 2C (Hot-Plug Controller on every port) - ECRC & Poison bit support - Data path protection - Memory (RAM) error correction - Advanced Error Reporting support - Port Status bits and GPIO available - Per port error diagnostics - Performance monitoring (per port payload & header counters) - JTAG AC/DC boundary scan - Fatal Error (FATAL_ERR#) output signal - INTA# output signal Version 1.2 2009 PEX 8618 The ExpressLane ™ PEX 8618 device offers PCI Express switching capability enabling users to add scalable high bandwidth non-blocking interconnection to a wide variety of applications including control planes, communication platforms, servers, storage systems and embedded systems. The PEX 8618 is well suited for fan-out, aggregation, peer-to-peer, and intelligent I/O module applications . Low Packet Latency & High Performance The PEX 8618 architecture supports packet cut-thru with a maximum latency of 140ns. This, combined with large packet memory and non-blocking internal switch architecture, provides full line rate on all ports for low-latency applications such as communications and servers. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a max payload size of 2048 bytes, enabling the user to achieve even higher throughout . Data Integrity The PEX 8618 provides end-to-end CRC protection (ECRC) and Poison bit support to enable designs that require guaranteed error-free packets. PLX also supports data path parity and memory (RAM) error correction as packets pass through the switch . Dual-Host and Fail-Over Support The PEX 8618 supports full non-transparent bridging (NTB) functionality to allow implementation of multi-host systems and intelligent I/O modules in applications which require redundancy support such as communications, storage, and servers. Non-transparent bridges allow systems to isolate host memory domains by presenting the processor subsystem as an endpoint rather than another memory system. Base address registers are used to translate addresses; doorbell registers are used to send interrupts between the address domains; and scratchpad registers are accessible from both address domains to allow inter-processor communication . Interoperability The PEX 8618 is designed to be fully compliant with the PCI Express Base Specification r2.0 and is backwards compatible to PCI Express Base Specification r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and polarity reversal. Furthermore, the PEX 8618 is designed for Microsoft Vista compliance. All PLX switches undergo thorough interoperability testing in PLX’s Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure compatibility with PCI Express devices in the market. Device Operation Configuration Flexibility The PEX 8618 provides several ways to configure its operations. The device can be configured through strapping pins, I 2C interface, CPU configuration cycles and/or an optional serial EEPROM. This allows for easy debug during the development phase and functional monitoring during the operation phase . |
Similar Part No. - PEX8618-BA50BCG |
|
Similar Description - PEX8618-BA50BCG |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |