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MCF51AC128CCFUE Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MCF51AC128CCFUE Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
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6 / 46 page  MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.4 MCF51AC256 Family Configurations Freescale Semiconductor 6 1.3.1 Feature List • 32-bit Version 1 ColdFire® central processor unit (CPU) — Up to 50.33 MHz at 2.7 V – 5.5 V — Provide 0.94 Dhrystone 2.1 DMIPS per MHz performance when running from internal RAM (0.76 DMIPS per MHz when running from flash) — Implements instruction set revision C (ISA_C) • On-chip memory — Up to 256 KB flash memory read/program/erase over full operating voltage and temperature — Up to 32 KB static random access memory (SRAM) — Security circuitry to prevent unauthorized access to SRAM and flash contents • Power-Saving Modes — Three low-power stop plus wait modes — Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode • System protection features — Watchdog computer operating properly (COP) reset — Low-voltage detection with reset or interrupt — Illegal opcode and illegal address detection with programmable reset or exception response — Flash block protection • Debug support — Single-wire background debug interface — Real-time debug support, with 6 hardware breakpoints (4 PC, 1 address pair and 1 data) that can be configured into a 1- or 2-level trigger — On-chip trace buffer provides programmable start/stop recording conditions plus support for continuous or PC-profiling modes — Support for real-time program (and optional partial data) trace using the debug visibility bus • V1 ColdFire interrupt controller (CF1_INTC) — Support of 40 peripheral I/O interrupt requests plus seven software (one per level) interrupt requests — Fixed association between interrupt request source and level plus priority, up to two requests can be remapped to the highest maskable level + priority — Unique vector number for each interrupt source — Support for service routine interrupt acknowledge (software IACK) read cycles for improved system performance • Multipurpose clock generator (MCG) — Oscillator (XOSC); loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz — FLL/PLL controlled by internal or external reference — Trimmable internal reference allows 0.2% resolution and 2% deviation • Analog-to-digital converter (ADC) |
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