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MCF5270AB100 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MCF5270AB100 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 42 page  MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Design Recommendations Freescale Semiconductor 10 will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. Drop VDD to 0 V. 2. Drop OVDD/VDDPLL supplies. 5.3 Decoupling • Place the decoupling caps as close to the pins as possible, but they can be outside the footprint of the package. • 0.1 μF and 0.01 μF at each supply input 5.4 Buffering • Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses when excessive loading is expected. See Section 7, “Electrical Characteristics.” 5.5 Pull-up Recommendations • Use external pull-up resistors on unused inputs. See pin table. 5.6 Clocking Recommendations • Use a multi-layer board with a separate ground plane. • Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator pins) as possible. • Do not run a high frequency trace around crystal circuit. • Ensure that the ground for the bypass capacitors is connected to a solid ground trace. • Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents in the vicinity of the crystal. • Tie the ground pin to the most solid ground in the system. • Do not connect the trace that connects the oscillator and the ground plane to any other circuit element. This tends to make the oscillator unstable. • Tie XTAL to ground when an external oscillator is clocking the device. 5.7 Interface Recommendations 5.7.1 SDRAM Controller 5.7.1.1 SDRAM Controller Signals in Synchronous Mode Table 3 shows the behavior of SDRAM signals in synchronous mode. |
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Similar Description - MCF5270AB100 |
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