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MMA81XXTKEG Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MMA81XXTKEG Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 49 page MMA81XXTKEG Sensors 6 Freescale Semiconductor 1.3 PIN FUNCTIONS The following paragraphs provide descriptions of the general function of each pin. 1.3.1 HCAP and VSS Power is supplied to the ASIC through BUSIN or BUSOUT and BUSRTN. The supply voltage is rectified internally and applied to the HCAP pin. An external capacitor connected to HCAP forms the positive supply for the integrated voltage regulator. VSS is supply return node. All VSS pins are internally connected to BUSRTN. To obtain specified performance, all VSS nodes should be connected to the BUSRTN node on the PWB. To ensure stability of the internal voltage regulator and meet DFMEA requirements, the connection from HCAP to the external capacitor should be as short as possible and should not be routed elsewhere on the printed wiring assembly. The voltage on HCAP is monitored. If the voltage falls below a specified level, the device will return the value zero in response to a short word Read Acceleration Data command, and report the undervoltage condition by setting the Undervoltage (U) flag. Should the undervoltage condition persist for more than one millisecond, the internal Power-On Reset (POR) circuit is activated and the device will not respond until the voltage at HCAP is restored to operating levels and the device has undergone post-reset initialization. 1.3.2 BUSIN The BUSIN pin is normally connected to the DSI bus and supports bidirectional communication with the master. MMA81XXEG supports reverse initialization for improved system fault tolerance. In the event that the DSI bus cannot support communication between the master and BUSIN pin, communication with the master may be conducted via the BUSOUT pin and the BUSIN pin can be used to access other DSI devices. 1.3.3 BUSOUT The BUSOUT pin is normally connected to the DSI bus for daisy-chained bus configurations. In support of fault tolerance at the system level, the BUSOUT pin can be used as an input for reverse initialization and data communication. The internal bus switch is always open following reset. The bus switch is closed when data bit D6 is set when an Initialization or Reverse Initialization command is received. 1.3.4 BUSRTN This pin provides the common return for power and signalling. 1.3.5 CREG The internal voltage regulator requires external capacitance to the VSS pin for stability. This should be a high grade capacitor without excessive internal resistance or inductance. An optional electrolytic capacitor may be required if a longer power down delay is required. Figure 1-3 illustrates the relationship between capacitance, series resistance and voltage regulator stability. Two CREG pins are provided for redundancy. It is recommended that both CREG pins are connected to the external capacitor(s) for best system reliability. Figure 1-3. Voltage Regulator Capacitance and Series Resistance CREG 1 μF100 μF ESR STABLE STABLE, UNACCEPTABLE 0 700 m Ω NOISE PERFORMANCE |
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