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MMA81XXTKEG Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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MMA81XXTKEG Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
8 / 49 page MMA81XXTKEG Sensors 8 Freescale Semiconductor Figure 1-5. VGND/DIN Connection Options 1.4 MODULE INTERCONNECT A typical satellite module configuration supporting daisy-chain configuration is shown in Figure 1-6. Capacitors C1 and C2 form a filter network for the internal voltage regulator. Two capacitors are shown for redundancy; this configuration improves reliability in the event of an open capacitor connection. A single 1 μF capacitor may be used in place of C1 and C2, however connection from the capacitor to both CREG pins is required. CHOLD stores energy during signal transitions on BUSIN and BUSOUT. The value of this capacitor is typically 1 μF; however, this depends upon data rates and bus utilization. Figure 1-6. Typical Satellite Module Diagram 1.5 DEVICE IDENTIFICATION Thirty-two OTP bits are factory-programmed with a unique serial number during the manufacturing and test. Five additional bits are factory-programmed to indicate the full-scale range and axis of sensitivity. Device identification data may be read at any time while the device is active. BUSRTN 1 nF CHASSIS 1.00 k Ω, 1% 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 MMA81XXTKEG/MMA82XXTKEG N/C VSS N/C VSS CREG BUSRTN VPP/TEST BUSIN CFIL DOUT VGND/DIN CLK BUSOUT HCAP VSS CREG BUSRTN GROUND-LOSS DETECTION DISABLED GROUND-LOSS DETECTION ENABLED (SINGLE-ENDED SYSTEMS ONLY) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 MMA81XXTKEG/MMA82XXTKEG N/C VSS N/C VSS CREG BUSRTN VPP/TEST BUSIN CFIL DOUT VGND/DIN CLK BUSOUT HCAP VSS CREG BUSRTN CHOLD BUSOUT C1 1 μF C2 1 μF N/C BUSIN SEE NOTE 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 MMA81XXTKEG/MMA82XXTKEG N/C VSS N/C VSS CREG BUSRTN VPP/TEST BUSIN CFIL DOUT VGND/DIN CLK BUSOUT HCAP VSS CREG NOTE: LEAVE OPEN OR CONNECT TO SIGNAL MONITOR. |
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