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HT45R35V Datasheet(PDF) 8 Page - Holtek Semiconductor Inc |
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HT45R35V Datasheet(HTML) 8 Page - Holtek Semiconductor Inc |
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8 / 42 page  HT45R35V Rev. 1.00 8 January 15, 2009 Functional Description Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de- coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc- tion to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter, PC controls the sequence in which the instructions stored in program ROM are exe- cuted and its contents specify full range of program memory. After accessing a program memory word to fetch an in- struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, a conditional skip execution, loading the PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt or return from a subroutine, the PC manipulates the pro- gram transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise the program will proceed with the next in- struction. The lower byte of the program counter, PCL is a read- able and writable register. Moving data into the PCL per- forms a short jump. The destination must be within the current Program Memory Page. When a control transfer takes place, an additional dummy cycle is required. T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 F e t c h I N S T ( P C ) E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 ) E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 ) E x e c u t e I N S T ( P C + 1 ) P C P C + 1 P C + 2 S y s t e m C l o c k O S C 2 ( R C o n l y ) P C Execution Flow Mode Program Counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial Reset 00000000000 External Interrupt 0 00000000100 External Interrupt 1 00000001000 Timer/Event Counter Overflow 00000001100 External RC Oscillation Converter Interrupt 00000010000 Skip Program Counter+2 Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *10~*0: Program Counter bits S10~S0: Stack register bits #10~#0: Instruction code bits @7~@0: PCL bits |
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