 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HT82K68A-L Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
|
||||||||||||||||||||||||||||||
HT82K68A-L Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
|
|
11 / 38 page  HT82K68E-L/HT82K68A-L Rev. 1.30 11 August 5, 2009 If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the WDT logic can be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user defined flags, which can be used to indicate some speci- fied status. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recom- mended, since the HALT will stop the system clock. WS2 WS1 WS0 Division Ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 WDTS (09H) Register The WDT overflow under normal operation will initialize ²chip reset² and set the status bit TO. An overflow in the HALT mode, initializes a ²warm reset² only when the pro- gram counter and stack pointer are reset to zero. To clear the contents of the WDT (including the WDT prescaler ), three methods are adopted; external reset (a low level to RESET), software instruction(s), or a HALT instruction. There are two types of software instructions; CLR WDT and CLR WDT1/CLR WDT2. Of these two types of instruction, only one can be active depending on the mask option -²CLR WDT times selection option². If the ²CLR WDT² is selected (ie. CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (ie. CLRWDT times equal two), these two in- structions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of the time-out. Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following... · The system oscillator will turn off but the WDT oscillator keeps running (if the WDT oscillator is selected). · The contents of the on–chip RAM and registers remain unchanged. · WDT and WDT prescaler will be cleared and recount again (if the WDT clock has come from the WDT oscillator). · All I/O ports maintain their original status. · The PDF flag is set and the TO flag is cleared. The system can leave the HALT mode by means of an external reset, interrupt, and external falling edge signal on port A and port C [0:3] or a WDT overflow. An exter- nal reset causes a device initialization and the WDT overflow performs a ²warm reset². Examining the TO and PDF flags, the reason for chip reset can be deter- mined. The PDF flag is cleared when system power-up or executing the CLR WDT instruction and is set when the HALT instruction is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the others keep their original status. On the other hand, awakening from an external interrupt (PC2), two sequences may happen. If the interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruc- tion. But if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. The port A or port C [0:3] wake-up can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. Once a wake-up event occurs, and the system clock comes from a crystal, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, the device will insert a dummy period after the wake-up. If the system clock comes from an RC oscillator, it continues operating immediately. If the wake-up results in next instruction execution, this will execute immediately after the dummy period is completed. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. |
Similar Part No. - HT82K68A-L |
|
Similar Description - HT82K68A-L |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
