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LTC2172-12 Datasheet(PDF) 8 Page - Linear Technology

Part # LTC2172-12
Description  12-Bit, 65Msps/40Msps/25Msps Low Power Quad ADCs
Download  34 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2172-12 Datasheet(HTML) 8 Page - Linear Technology

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LTC2172-12/
LTC2171-12/LTC2170-12
8
21721012fa
TIMING DIAGRAMS
2-Lane Output Mode, 16-Bit Serialization
2-Lane Output Mode, 14-Bit Serialization
217212 TD01
tAP
N + 1
N
ANALOG
INPUT
ENC–
DCO–
FR–
ENC+
DCO+
FR+
OUT#A+
SAMPLE N-6
SAMPLE N-5
OUT#A–
OUT#B+
OUT#B–
SAMPLE N-4
tFRAME
tDATA
tSER
tSER
tPD
D3
D1
DX*
0
D11
D9
D7
D5
D3
D1
DX*
0
D11
D9
D7
D2
D0
DY*
0
D10
D8
D6
D4
D2
D0
DY*
0
D10
D8
D6
tENCH
tENCL
tSER
*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
217212 TD02
tAP
N + 2
N + 1
N
ANALOG
INPUT
ENC–
DCO–
FR–
ENC+
DCO+
FR+
OUT#A+
NOTE THAT IN THIS MODE, FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC–
SAMPLE N-6
SAMPLE N-5
OUT#A–
OUT#B+
OUT#B–
SAMPLE N-3
SAMPLE N-4
tFRAME
tDATA
tSER
tSER
tPD
D5
D3
D1
DX* D11
D9
D7
D5
D3
D1
DX* D11
D9
D7
D5
D3
D1
DX* D11
D9
D7
D4
D2
D0
DY* D10
D8
D6
D4
D2
D0
DY* D10
D8
D6
D4
D2
D0
DY* D10
D8
D6
tENCH
tENCL
tSER
*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.


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