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LTC2172CUKG-14PBF Datasheet(PDF) 1 Page - Linear Technology |
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LTC2172CUKG-14PBF Datasheet(HTML) 1 Page - Linear Technology |
1 / 32 page LTC2172-14/ LTC2171-14/LTC2170-14 1 21721014f TYPICAL APPLICATION DESCRIPTION 14-Bit, 65Msps/40Msps/ 25Msps Low Power Quad ADCs The LTC®2172-14/LTC2171-14/LTC2170-14 are 4-channel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 73.7dB SNR and 90dB spurious free dynamic range (SFDR). An ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. DC specifications include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transi- tion noise is a low 1.2LSBRMS. The digital outputs are serial LVDS to minimize the num- ber of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. LTC2172-14, 65Msps, 2-Tone FFT, fIN = 70MHz and 75MHz FEATURES APPLICATIONS n 4-Channel Simultaneous Sampling ADC n 73.7dB SNR n 90dB SFDR n Low Power: 311mW/202mW/162mW Total, 78mW/51mW/41mW per Channel n Single 1.8V Supply n Serial LVDS Outputs: One or Two Bits per Channel n Selectable Input Ranges: 1VP-P to 2VP-P n 800MHz Full Power Bandwidth Sample-and-Hold n Shutdown and Nap Modes n Serial SPI Port for Configuration n Pin-Compatible 14-Bit and 12-Bit Versions n 52-Pin (7mm × 8mm) QFN Package n Communications n Cellular Base Stations n Software Defined Radios n Portable Medical Imaging n Multichannel Data Acquisition n Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. DATA SERIALIZER ENCODE INPUT SERIALIZED LVDS OUTPUTS 1.8V VDD 1.8V OVDD OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B DATA CLOCK OUT FRAME OGND GND 217214 TA01 S/H CHANNEL 1 ANALOG INPUT 14-BIT ADC CORE S/H CHANNEL 2 ANALOG INPUT 14-BIT ADC CORE S/H CHANNEL 3 ANALOG INPUT 14-BIT ADC CORE S/H CHANNEL 4 ANALOG INPUT 14-BIT ADC CORE PLL FREQUENCY (MHz) 0 –100 –110 –120 –70 –60 –80 –90 –50 –30 –40 –20 –10 0 10 20 30 217214 TA01b |
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