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LTC2264IUJ-12PBF Datasheet(PDF) 6 Page - Linear Technology |
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LTC2264IUJ-12PBF Datasheet(HTML) 6 Page - Linear Technology |
6 / 32 page 6 22654312f LTC2265-12/ LTC2264-12/LTC2263-12 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS LTC2265-12 LTC2264-12 LTC2263-12 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 82 98 52 63 42 50 mA IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 11 20 15 28 18 31 10 19 15 28 18 31 10 18 14 27 17 31 mA mA mA mA PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 167 184 175 198 209 232 112 128 121 144 146 169 94 108 101 124 121 146 mW mW mW mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 60 60 60 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled (No Increase for Sleep Mode) 20 20 20 mW TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS LTC2265-12 LTC2264-12 LTC2263-12 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX fS Sampling Frequency (Notes 10, 11) l 5 65 5 45 5 25 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 7.3 2 7.69 7.69 100 100 11.88 2 12.5 12.5 100 100 19 2 20 20 100 100 ns ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 7.3 2 7.69 7.69 100 100 11.88 2 12.5 12.5 100 100 19 2 20 20 100 100 ns ns tAP Sample-and-Hold Acquisition Delay Time 000 ns |
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