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LTC2263CUJ-12PBF Datasheet(PDF) 1 Page - Linear Technology |
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LTC2263CUJ-12PBF Datasheet(HTML) 1 Page - Linear Technology |
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1 / 32 page  LTC2265-12/ LTC2264-12/LTC2263-12 1 22654312f TYPICAL APPLICATION DESCRIPTION 12-Bit, 65Msps/40Msps/ 25Msps Low Power Dual ADCs The LTC®2265-12/LTC2264-12/LTC2263-12 are 2-channel, simultaneous sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 71dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS. The digital outputs are serial LVDS to minimize the num- ber of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. LTC2265-12, 65Msps, 2-Tone FFT, fIN = 70MHz and 75MHz FEATURES APPLICATIONS n 2-Channel Simultaneous Sampling ADC n 71dB SNR n 90dB SFDR n Low Power: 167mW/112mW/94mW Total n 83mW/56mW/47mW per Channel n Single 1.8V Supply n Serial LVDS Outputs: 1 or 2 Bits per Channel n Selectable Input Ranges: 1VP-P to 2VP-P n 800MHz Full Power Bandwidth S/H n Shutdown and Nap Modes n Serial SPI Port for Configuration n Pin Compatible 14-Bit and 12-Bit Versions n 40-Pin (6mm × 6mm) QFN Package n Communications n Cellular Base Stations n Software Defined Radios n Portable Medical Imaging n Multichannel Data Acquisition n Nondestructive Testing CH.1 ANALOG INPUT CH.2 ANALOG INPUT ENCODE INPUT 226512 TA01 GND OGND + – S/H + – S/H 12-BIT ADC CORE 12-BIT ADC CORE PLL DATA SERIALIZER SERIALIZED LVDS OUTPUTS 1.8V 1.8V VDD OVDD OUT1A OUT1B OUT2A OUT2B DATA CLOCK OUT FRAME FREQUENCY (MHz) 0 –100 –110 –120 –70 –60 –80 –90 –50 –30 –40 –20 –10 0 10 20 30 226512 TA02 L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. |
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