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GA1086 Datasheet(PDF) 10 Page - TriQuint Semiconductor

Part # GA1086
Description  11-Output Clock Buffer
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Manufacturer  TRIQUINT [TriQuint Semiconductor]
Direct Link  http://www.triquint.com
Logo TRIQUINT - TriQuint Semiconductor

GA1086 Datasheet(HTML) 10 Page - TriQuint Semiconductor

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GA1086
For additional information and latest specifications, see our website: www.triquint.com
10
AC Specifications
Notes:
Q0
Q1
Q2
Q10
FBIN
CLK
R1
R2
+5 V
R1
R2
+5 V
R1
R2
+5 V
R1
R2
+5 V
R1
R2
+5 V
Y
X
50
Z
Z
R1 = 160
R2 = 71
Y + Z = X
Input Clocks
Min
Typ
Max
Unit
FIN
CLK frequency
30
67
MHz
tCP
CLK period
14.9
33
ns
tCPW
CLK pulse width
3.0
ns
tIR
Input rise time (0.8 V – 2.0 V)
2.0
ns
Output Clocks
Min
Typ
Max
Unit
tOR
Output rise time (0.8 V – 2.0 V) 0.15
1.4
ns
tOF
Output fall time (0.8 V – 2.0 V)
0.15
1.4
ns
tPD11
CLK Î to FBIN Î (MC500)
–850
–350
+150
ps
tPD21,2
CLK Î to FBIN Î (MC1000)
–1350
–350
+650
ps
tSKEW12,3 Q1–Q9 and FBOUT (0.8V)
–125
+125
ps
tSKEW12,3 Q1–Q9 and FBOUT (1.5V)
–125
+125
ps
tSKEW12,3 Q1–Q9 and FBOUT (2.0V)
–125
+125
ps
tSKEW22,3 Q/2 Output skew
0.6
1.2
ns
tW 4
Output window
100
250
ps
tCYC 5
Duty-cycle variation
1.0
ns
tSYNC 6
Synchronization time
200
500
µs
tJIT 7
Period-to-period jitter
75
ps
Figure 11. Switching Waveforms
Buffer Configuration (FBIN = FBOUT)
t PD1,2
t JR
tCPW
(INDIVIDUALLY)
REFCLK
FBIN
Q0 – Q10
tCPW
t PERIOD
t JP
Figure 12. AC Test Circuit
(Supply voltage: +5 V + 5%, Ambient temp: 0
°C to +70 °C)
Notes: 1. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
2. tPD and tSKEW are tested with an input clock having a rise time of 0.5 ns (0.8 V to 2.0 V).
3. The output skew is measured from the middle of the output window, tW. The maximum skew is guaranteed across all voltages and
temperatures.
4. tW specifies the width of the window in which outputs Q1–Q9 switch.
5. This specification represents the deviation from 50/50 on the outputs; it is sampled periodically but is not guaranteed.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and a connection from one of the
outputs to FBIN.
7. Jitter is specified as a peak-to-peak value.


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