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Application circuit for the TGF4118-EPU at 2.3 GHz

The FET is soldered using AuSn solder at 300 C for 30 secs. Input and Output matching networks are

0.381 mm ZrSn Tioxide substrates (Er = 38). The design load impedance is between 4

Ω and 5 Ω with

the 6 pF output capacitance of the FETincluded in the output network. For further explanation refer to

the application note “Designing High Efficiency Amplifiers using HFETs”

. The carrier plate is 0.51 mm

gold plated copper molybdenum. Gold wire (0.018 mm) is used for the bonds. Four gate bonds are

required with a length of 0.42 mm. Eight drain bonds are required with a length of 0.42 mm. Bondwire

end points on the FET are in the middle of the bond pads. Refer to the figures above for bondwire

locations. Connection between the 50 ohm line input to the input match is made by a parallel RC

network. R1 in this network is 10 ohms, and C1 is 5.6 pF. The components used are surface mount

0603 piece parts.