TQ9147B

Data Sheet

8

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Drain current for the second stage is injected through L1 (47

nH), which acts as an RF choke on the high power DC feed line.

As stated above, C1 is the bypass cap for the high impedance

side of L1.

Power down Function

To fully turn off the PA when not transmitting, a PMOS FET

(PFET) switch can be used to control the drain bias to the PA.

There are several acceptable models available on the market,

such as the IRF7604 from International Rectifier, or any device

this type is that it protects the PA from inadvertently powering up

the device incorrectly. Since depletion-mode FETs are used in

the PA, care must be taken to insure that the gate bias is fully

will flow, which could damage or destroy the IC. A feature

included in the Maxim charge pump allows for a separate

control output to run the PFET. This control line holds the PFET

off until the gate bias voltage has stabilized.

RF Power Control

There are three methods of controlling the output power from

the TQ9147. All three methods can provide a minimum 25 dB of

control range for the device, which exceeds the requirements of

IS-19.

The first method is to vary the gate bias voltages. Though this

approach has the advantage of increased efficiency at lower

output power levels, it is hampered by two problems. First, both

gate voltages must be varied. Since each stage typically

requires a different bias point, the control circuit must monitor

both bias points, thereby complicating the design.

The second drawback is that most charge pumps, including

those recommended above, require large capacitors on the

output for filtering and stability. Such large cap values may not

allow full compliance with the required 20 mS transition spec

between any two power levels.

The second method is to vary the input power level. Though

this can be done with a simple attenuator between the driver

amp and the PA, the response is very non-linear, as the PA

must first come out of saturation before the output power can

change. Once out of saturation, the first stage is class A biased,

which means that the drain current is constant regardless of

power settings. The addition of an attenuator also adds to the

expense of the parts list and to the board size equation, and

increases the insertion loss the driver amp must overcome.

The third, and preferred, method is to vary the drain supply

voltage to the first stage. By forcing the first stage bias lower,

the first stage is always heavily saturated, thus saving battery

power. Since the second stage is biased class AB, drain current

to that stage lowers as the drive level decreases. This method

optimizes battery savings over the other approaches. The

simplest implementation of this technique would be to

incorporate a second PFET to control the first stage drain. This

circuit can be realized buy utilizing a dual PFET such as the

a single SO-8 package. By cascoding the two FETs, one

implements a master on/off function while the second controls

only the first stage drain bias. This technique also fits very well

with the active gate biasing circuit that was recommended

previously.