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34AA02 Datasheet(PDF) 4 Page - Microchip Technology |
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34AA02 Datasheet(HTML) 4 Page - Microchip Technology |
4 / 32 page 34AA02/34LC02 DS22029E-page 4 2010 Microchip Technology Inc. TABLE 1-2: AC SPECIFICATIONS AC CHARACTERISTICS VCC = +1.7V to +5.5V Industrial (I): TA = -40°C to +85°C Automotive (E):TA = -40°C to +125°C Param. No. Symbol Characteristic Min. Max. Units Conditions 1FCLK Clock frequency — — — 100 400 1000 kHz 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 2THIGH Clock high time 4000 600 500 — — — ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 3TLOW Clock low time 4700 1300 500 — — — ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 4TR SDA and SCL rise time (Note 1) — — — 1000 300 300 ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 5TF SDA and SCL fall time (Note 1) — — — 1000 300 300 ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 6THD:STA Start condition hold time 4000 600 250 — — — ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 7TSU:STA Start condition setup time 4700 600 250 — — — ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 8THD:DAT Data input hold time 0 — ns (Note 2) 9TSU:DAT Data input setup time 250 100 100 — — — ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 10 TSU:STO Stop condition setup time 4000 600 250 — — — ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 11 TSU:WP WP setup time 4000 600 600 — — — ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 12 THD:WP WP hold time 4700 600 600 — — — ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 13 TAA Output valid from clock (Note 2) — — — 3500 900 400 ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 14 TBUF Bus free time: Time the bus must be free before a new transmission can start 1300 4700 — — — ns 1.7V VCC < 1.8V 1.8V VCC 5.5V 2.5V VCC 5.5V (34LC02) 16 TSP Input filter spike suppression (SDA and SCL pins) — 50 ns All except 34LC02 (Note 1 and Note 3) 17 TWC Write cycle time (byte or page) — 5 ms — 18 — Endurance 1M — cycles 25°C, VCC = 5.5V, Block mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppres- sion. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. |
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