CY8CLED02
Document Number: 001-13704 Rev. *C
Page 3 of 39
EZ-Color™ Functional Overview
Cypress's EZ-Color family of devices offers the ideal control
solution for High Brightness LED applications requiring intel-
ligent dimming control. EZ-Color devices combine the power and
flexibility of PSoC (Programmable System-on-Chip™); with
Cypress' PrISM (precise illumination signal modulation) drive
technology providing lighting designers a fully customizable and
integrated lighting solution platform.
The EZ-Color family supports a range of independent LED
channels from 4 channels at 32 bits of resolution each, up to 16
channels at 8 bits of resolution each. This enables lighting
designers the flexibility to choose the LED array size and color
quality. PSoC Designer software, with lighting specific drivers,
can significantly cut development time and simplify implemen-
tation of fixed color points through temperature, optical, and LED
binning compensation. EZ-Color's virtually limitless analog and
digital customization enables the simple integration of features
in addition to intelligent lighting, such as Battery Charging, Image
Stabilization, and Motor Control during the development
process. These features, along with Cypress's best-in-class
quality and design support, make EZ-Color the ideal choice for
intelligent HB LED control applications.
Target Applications
■ LCD Backlight
■ Large Signs
■ General Lighting
■ Architectural Lighting
■ Camera/Cell Phone Flash
■ Flashlights
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and an IMO
(internal main oscillator) and an ILO (internal low speed oscil-
lator). The CPU core, called the M8C, is a powerful, four MIPS,
8-bit Harvard architecture microprocessor with speeds up to 24
MHz.
System Resources provide additional capability, such as digital
clocks to increase the flexibility of the PSoC; I2C functionality for
implementing an I2C master, slave, or multi-master; an internal
voltage reference that provides an absolute value of 1.3V to a
number of PSoC subsystems; a switch mode pump (SMP) that
generates normal operating voltages off a single battery cell; and
various system resets supported by the M8C.
The Digital System is composed of an array of digital blocks,
which can be configured into any number of digital peripherals.
The digital blocks can be connected to the GPIO through a series
of global busses that can route any signal to any pin, freeing
designers from the constraints of a fixed peripheral controller.
The Analog System consists of four analog blocks, supporting
comparators, and analog-to-digital conversion up to 10 bits of
precision.
The Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit periph-
erals, which are called user module references. Digital peripheral
configurations include those listed below.
■ PrISM (8 to 32 bit)
■ PWMs (8 to 32 bit)
■ PWMs with dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity
■ SPI master and slave
■ I2C slave, master, multi-master (1 available as a System
Resource)
■ Cyclical redundancy checker/generator (8 to 32 bit)
■ IrDA (up to 4)
■ Generators (8 to 32 bit)
Connect the digital blocks to any GPIO through a series of global
busses that can route any signal to any pin. The busses also
allow for signal multiplexing and for performing logic operations.
This configurability frees your designs from the constraints of a
fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by device family. This allows you the optimum
choice of system resources for your application. Family
resources are shown in the table titled EZ-Color Device Charac-
teristics.
Figure 1. Digital System Block Diagram
DIGITAL SYSTEM
To System Bus
Digital Clocks
From Core
Digital PSoC Block Array
To Analog
System
8
8
8
8
Row 0
DBB00
DBB01
DCB02
DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 1
Port 0
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