CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Document #: 38-05356 Rev. *G
Page 10 of 32
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for byte write operations, see Truth Table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
The data written during the write operation is controlled by BWX
signals.
The
CY7C1461AV33/CY7C1463AV33/CY7C1465AV33
provides byte write capability that is described in the truth table.
Asserting the (WE) with the selected byte write select input
selectively writes to only the desired bytes. Bytes not selected
during a byte write operation remains unaltered. A synchronous
self timed write mechanism is provided to simplify the write
operations. Byte write capability is included to greatly simplify
Read/Modify/Write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is
a common IO device, data must not be driven into the device
when the outputs are active. The OE can be deasserted HIGH
before presenting data to the DQs and DQPX inputs. This
tri-states the output drivers. As a safety precaution, DQs and
DQPX are automatically tri-stated during the data portion of a
write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 has an
on-chip burst counter that provides the ability to supply a single
address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in the Single Write
Accesses section. When ADV/LD is driven HIGH on the subse-
quent clock rise, the chip enables (CE1, CE2, and CE3) and WE
inputs are ignored and the burst counter is incremented. The
correct BWX inputs must be driven in each cycle of the burst
write, to write the correct bytes of data.
.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. When in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, and CE3,
must remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
100
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
tZZI
ZZ active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
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