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TMS320C5504AZCH12 Datasheet(PDF) 6 Page - Texas Instruments |
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TMS320C5504AZCH12 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 128 page  TMS320C5504 SPRS659 – JANUARY 2010 www.ti.com 2 Device Overview 2.1 Device Characteristics Table 2-1, provides an overview of the TMS320C5504 DSP. The tables show significant features of the C5504 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. For more detailed information on the actual device P/N and maximum device operating frequency, see Section 2.6.2, Device and Development-Support Tool Nomenclature. Table 2-1. Characteristics of the C5504 Processor HARDWARE FEATURES C5504 Asynchronous (8/16-bit bus width) SRAM, Peripherals External Memory Interface (EMIF) Flash (NOR, NAND), Not all peripheral pins are SDRAM and Mobile SDRAM (16-bit bus width)(1) available at the same time Flash Cards 2 MMC/SD (for more detail, see the Device Configurations Four DMA controllers each with four channels, DMA section). for a total of 16 channels 2 32-Bit General-Purpose (GP) Timers Timers 1 Additional Configurable as a 32-Bit GP Timer and/or a Watchdog UART 1 (with RTS/CTS flow control) SPI 1 with 4 chip selects I2C 1 (Master/Slave) I2S 4 (Two Channel, Full Duplex Communication) USB 2.0 (Device only) High- and Full-Speed Device 256 byte read/write buffer, max 50-MHz clock for SD cards, MMC/SD and signaling for DMA transfers Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply) General-Purpose Input/Output Port (GPIO) Up to 26 pins (with 1 Additional General-Purpose Output (XF)) Size (Bytes) 256 KB RAM, 128KB ROM • 64KB On-Chip Dual-Access RAM (DARAM) On-Chip Memory Organization • 192 KB On-Chip Single-Access RAM (SARAM) • 128KB On-Chip Single-Access ROM (SAROM) JTAGID Register JTAG BSDL_ID see Figure 5-33 (Value is: 0009_702F) 1.05-V Core 60 or 75 MHz CPU Frequency MHz 1.3-V Core 100, 120 MHz 1.05-V Core 16.67, 13.3 ns Cycle Time ns 1.3-V Core 10, 8.33 ns 1.05 V (60, 75 MHz) Core (V) Voltage 1.3 V (100, 120 MHz) I/O (V) 1.8 V, 2.5 V, 2.8 V, 3.3 V 1.3 V, TBD mA max current for PLL (VDDA_PLL) and power LDO ANA_LDO management circuits (VDDA_ANA) Active @ Room Temp 25°C, 75% DMAC + 0.15 mW/MHz @ 1.05 V, 60 or 75 MHz Power Characterization 25% ADD (Typical Sine Wave Data 0.22 mW/MHz @ 1.3 V, 100 or 120 MHz Switching) Active @ Room Temp 25°C, 75% DMAC + 0.14 mW/MHz @ 1.05 V, 60 or 75MHz 25% NOP (Typical Sine Wave Data 0.22 mW/MHz @ 1.3 V, 100 or 120 MHz Switching) Standby (Master Clock Disabled) @ Room 0.26 mW @ 1.05 V Temp 25°C (DARAM and SARAM in Active 0.44 mW @ 1.3 V Mode) (1) For more compatibility with SDRAM devices, see Section 5.9 , External Memory Interface (EMIF). 6 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C5504 |
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