UCD9224

www.ti.com

SLVSA35 – JANUARY 2010

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ERROR AMPLIFIER INPUTS EAPn, EANn

Common mode voltage each pin

–0.15

1.848

V

Internal error voltage range

–256

248

mV

EAP-EAN

Error voltage digital resolution

AFE_GAIN field of CLA_GAINS = 3

1

mV

Input Impedance

Ground reference

0.5

1.5

3

M

Ω

Input offset current

1 k

Ω source impedence

–5

5

µA

Vref 10-bit DAC

Reference voltage setpoint

0

1.6

V

Reference voltage resolution

1.56

mV

Voltage indicating open pin

ADDR-0, ADDR-1 open

2.37

V

Voltage indicating shorted pin

ADDR-0, ADDR-1 short to ground

0.36

V

Measurement range for voltage monitoring

0

2.5

V

CS-1B, CS-2A, CS-3A

Over-current comparator threshold voltage

Inputs: CS-1A, CS-1B, CS-2A, CS-3A

0.032

2

V

Over-current comparator threshold voltage

Inputs: CS-1A, CS-1B, CS-2A, CS-3A

31.25

mV

range

ADCref

External reference input

1.8

V33A

V

Int. temperature sense accuracy

Over range from 0°C to 125°C

–5

5

°C

INL

ADC integral nonlinearity

–2.5

2.5

mV

Input leakage current

3V applied to pin

100

nA

Input impedance

Ground reference

8

M

Ω

Current Sense Input capacitance

10

pF

DIGITAL INPUTS/OUTPUTS

DGND1

Low-level output voltage

V

+0.25

High-level output voltage

V

–0.6V

High-level input voltage

2.1

3.6

V

Low-level input voltage

1.4

V

SYSTEM PERFORMANCE

Voltage where device comes out of reset

2.3

2.4

V

Pulse width needed for reset

nRESET pin

2

µs

Setpoint reference accuracy

–10

10

mV

AFEgain = 4, 1V input to EAP/N measured at

Setpoint reference accuracy over temperature –40°C to 125°C

–20

20

mV

Differential offset between gain settings

AFEgain = 4 compared to AFEgain = 1, 2, or 8

–4

4

mV

240 + 1

Digital compensator delay

240

switching

ns

cycle

Switching frequency

15.260

2000

kHz

Duty

Max and Min duty cycle

0%

100%

0.25

V/ms

Retention of configuration parameters

100

Years

Write_Cycles

Number of nonvolatile erase/write cycles

20

K cycles

(1)

See the UCD92xx PMBus Command Reference for the description of the AFE_GAIN field of CLA_GAINS command.

(2)

Can be disabled by setting to '0'0

(3)

(4)

(5)

With default device calibration. PMBus calibration can be used to improve the regulation tolerance

Copyright © 2010, Texas Instruments Incorporated

Submit Documentation Feedback

3