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UCD9248 Datasheet(PDF) 5 Page - Texas Instruments |
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UCD9248 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 32 page  UCD9248 www.ti.com SLVSA33 – JANUARY 2010 HARDWARE FAULT DETECTION LATENCY The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer. PARAMETER TEST CONDITIONS MAX UNIT tFAULT Time to disable DPWM output based on corresponding 15 + 3 × High level on FAULT pin µs active FLTpin NumPhases Time to disable the first DPWM output based on Step change in CS voltage from 0V to Switch 4 internal analog comparator fault 2.5V Cycles tCLF Time to disable all remaining DPWM and SRE outputs Step change in CS voltage from 0V to 10 + 3 × configured for the voltage rail after an internal analog µs 2.5V NumPhases comparator fault PMBUS/SMBUS/I2C The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and PMBus are shown below. I 2C/SMBus/PMBus TIMING CHARACTERISTICS TA = –40°C to 125°C, 3V < V33 < 3.6V, typical values at TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSMB SMBus/PMBus operating frequency Slave mode; SMBC 50% duty cycle 10 1000 kHz fI2C I2C operating frequency Slave mode; SCL 50% duty cycle 10 1000 kHz t(BUF) Bus free time between start and stop 4.7 µs t(HD:STA) Hold time after (repeated) start 0.26 µs t(SU:STA) Repeated start setup time 0.26 µs t(SU:STO) Stop setup time 0.26 µs t(HD:DAT) Data hold time Receive mode 0 ns t(SU:DAT) Data setup time 50 ns t(TIMEOUT) Error signal/detect See (1) 35 ms t(LOW) Clock low period 0.5 µs t(HIGH) Clock high period See (2) 0.26 50 µs t(LOW:SEXT) Cumulative clock low slave extend time See (3) 25 ms tFALL Clock/data fall time See (4) 120 ns tRISE Clock/data rise time See (5) 120 ns (1) The UCD9248 times out when any clock low exceeds t(TIMEOUT). (2) t(HIGH), max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9248 that is in progress. (3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. (4) Rise time tRISE = VILMAX – 0.15) to (VIHMIN + 0.15) (5) Fall time tFALL = 0.9 V33 to (VILMAX – 0.15) Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 |
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