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MMA5206WR2 Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc

Part # MMA5206WR2
Description  PSI5 Inertial Sensor
Download  61 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MMA5206WR2 Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc

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Sensors
4
Freescale Semiconductor
MMA52xxWR
Preliminary
1
PIN CONNECTIONS
Figure 4. Top View, 16-Pin QFN Package
Table 1. Pin Description
Pin
Pin
Name
Formal Name
Definition
1
VCC
Supply
This pin is connected to the PSI5 power and data line through a resistor and supplies power to the device. An external capac-
itor must be connected between this pin and VSS. Reference Figure 1.
2
VSS
Digital GND
This pin is the power supply return node for the digital circuitry.
3
IDATA
Response
Current
This pin is connected to the PSI5 power and data line through a resistor and modulates the response current for PSI5 com-
munication. Reference Figure 1.
4
VSS
Digital GND
This pin is the power supply return node for the digital circuitry.
5
PCM
PCM
Output
This pin provides a 4 MHz PCM signal proportional to the acceleration data for test purposes. The output can be enabled via
OTP. Reference Section 3.5.3.7. If unused, this pin must be left unconnected.
6
SCLK
SPI Clock
This input pin provides the serial clock to the SPI port for test purposes. An internal pull-down device is connected to this pin.
This pin must be grounded or left unconnected in the application.
7
DOUT
SPI Data Out
This pin functions as the serial data output from the SPI port for test purposes. This pin must be left unconnected in the appli-
cation.
8
DIN
SPI Data In
This pin functions as the serial data input to the SPI port for test purposes. An internal pull-down device is connected to this
pin. This pin must be grounded or left unconnected in the application.
9
VREG
Digital
Supply
This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between
this pin and VSS. Reference Figure 1.
10
CS
Chip Select
This input pin provides the chip select to the SPI port for test purposes. An internal pull-up device is connected to this pin.This
pin must be left unconnected in the application.
11
VREGA
Analog
Supply
This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between
this pin and VSSA. Reference Figure 1.
12
VSSA
Analog GND
This pin is the power supply return node for the analog circuitry.
13
VBUF
Power
Supply
This pin is connected to a buffer regulator for the internal circuitry. The buffer regulator supplies both the analog (VREGA) and
digital (VREG) supplies to provide immunity from EMC and supply dropouts on VCC. An external capacitor must be connected
between this pin and VSS. Reference Figure 1.
14
TEST
Test Pin
This pin is must be grounded or left unconnected in the application.
15
BUS_SW
Bus Switch
Gate Drive
This pin is the drive for a low side daisy chain switch. When daisy chain mode is enabled, this pin is connected to the gate of
an n-channel FET which connects VSS to VSS_OUT. Reference Figure 1. If unused, this pin must be left unconnected.
16
VSSA
Analog GND
This pin is the power supply return node for the analog circuitry.
17
PAD
Die Attach Pad
This pin is the die attach flag, and is internally connected to VSS. Reference Section 7 for die attach pad connection details.
VCC
VSS
VREGA
CS
VREG
VSS
IDATA
VSSA
1
2
3
4
5
6
7
8
12
11
10
9
16 15 14 13
17


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