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MPC8323E Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MPC8323E Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
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6 / 82 page  MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 6 Freescale Semiconductor Electrical Characteristics 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8323E. The MPC8323E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings1 Characteristic Symbol Max Value Unit Notes Core supply voltage VDD –0.3 to 1.26 V — PLL supply voltage AVDDn –0.3 to 1.26 V — DDR1 and DDR2 DRAM I/O voltage GVDD –0.3 to 2.75 –0.3 to 1.98 V— PCI, local bus, DUART, system control and power management, I2C, SPI, MII, RMII, MII management, and JTAG I/O voltage OVDD –0.3 to 3.6 V — Input voltage DDR1/DDR2 DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2 DDR1/DDR2 DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2 Local bus, DUART, CLKIN, system control and power management, I2C, SPI, and JTAG signals OVIN –0.3 to (OVDD + 0.3) V 3 PCI OVIN –0.3 to (OVDD + 0.3) V 5 Storage temperature range TSTG –55 to 150 °C— Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. |
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