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HYMD232G726DP8-H Datasheet(PDF) 10 Page - Hynix Semiconductor

Part # HYMD232G726DP8-H
Description  184pin Registered DDR SDRAM DIMMs
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HYMD232G726DP8-H Datasheet(HTML) 10 Page - Hynix Semiconductor

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Rev. 1.1 /May. 2005
10
184pin Registered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
512MB, 64Mb x 72 ECC Registered DIMM : HYMD264G726D[P]8[M]
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol
Test Condition
Speed
Unit
Note
-K
-H
-L
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
1640
1640
1550
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control
inputs changing once per clock cycle
1820
1820
1685
mA
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
830
830
830
mA
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
1370
1370
1235
mA
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
920
920
920
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
1370
1370
1280
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
2360
2360
2135
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing
twice per clock cycle
2360
2360
2135
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
1970
1970
1835
mA
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
404
404
404
mA
Low Power
377
377
377
mA
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
2810
2810
2585
mA


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