Rev. 1.2 / May. 2005

10

128MB, 16M x 64 Unbuffered DIMM: HYMD232646D[P]6[J]

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol

Test Condition

Speed

Unit

Note

DDR400

DDR333 DDR266A DDR266B

IDD0

One bank; Active - Precharge; tRC=tRC(min);

tCK=tCK(min); DQ,DM and DQS inputs changing

twice per clock cycle; address and control inputs

changing once per clock cycle

360

320

280

280

mA

IDD1

One bank; Active - Read - Precharge; Burst

Length=2; tRC=tRC(min); tCK=tCK(min); address

and control inputs changing once per clock cycle

400

400

360

360

mA

IDD2P

All banks idle; Power down mode; CKE=Low,

tCK=tCK(min)

40

40

40

40

mA

IDD2F

/CS=High, All banks idle; tCK=tCK(min); CKE=

High; address and control inputs changing once

per clock cycle. VIN=VREF for DQ, DQS and DM

240

200

160

160

mA

IDD3P

One bank active; Power down mode; CKE=Low,

tCK=tCK(min)

60

60

60

60

mA

IDD3N

/CS=HIGH; CKE=HIGH; One bank; Active-Pre-

charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM

and DQS inputs changing twice per clock cycle;

Address and other control inputs changing once

per clock cycle

200

180

160

160

mA

IDD4R

Burst=2; Reads; Continuous burst; One bank

active; Address and control inputs changing once

per clock cycle; tCK=tCK(min); IOUT=0mA

800

760

680

680

mA

IDD4W

Burst=2; Writes; Continuous burst; One bank

active; Address and control inputs changing once

per clock cycle; tCK=tCK(min); DQ, DM and DQS

inputs changing twice per clock cycle

800

760

680

680

mA

IDD5

tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,

10*tCK for DDR266A & DDR266B at 133Mhz; dis-

tributed refresh

600

600

560

560

mA

IDD6

CKE=<0.2V; External clock on; tCK

=tCK(min)

Normal

12

12

12

12

mA

Low Power

6

66

6

mA

IDD7

Four bank interleaving with BL=4 Refer to the fol-

lowing page for detailed test condition

1000

960

880

880

mA