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HYMP41GP72CNP4L-Y5 Datasheet(PDF) 2 Page - Hynix Semiconductor

Part # HYMP41GP72CNP4L-Y5
Description  240pin DDR2 VLP Registered DIMMs
Download  27 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HYMP41GP72CNP4L-Y5 Datasheet(HTML) 2 Page - Hynix Semiconductor

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Rev. 0.2 / May. 2008
1
240pin DDR2 VLP Registered DIMMs
FEATURES
ADDRESS TABLE
Density Organization Ranks
SDRAMs
# of
DRAMs
# of row/bank/column Address
Refresh
Method
1GB
128Mb x 72
1
128Mb x 8
9
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
8K / 64ms
2GB
256Mb x 72
1
256Mb x 4
18
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
4GB
512Mb x 72
2
256Mb x 4
36
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64m
8GB
1Gb x 72
4
256Mb x 4
72
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64m
JEDEC standard 1.8V +/- 0.1V Power Supply
•VDDQ : 1.8V +/- 0.1V
All inputs and outputs are compatible with SSTL_1.8 interface
•4 Bank architecture
•Posted CAS
Programmable CAS Latency 3 , 4 , 5
OCD (Off-Chip Driver Impedance Adjustment)
•ODT (On-Die Termination)
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both sequential and interleave mode
Average Auto Refresh Period 7.8us under TCASE 85℃, 3.9us at 85℃ < TCASE ≤ 95 ℃
High Temperature Self-Refresh Entry enablble features
PASR(Partial Array Self- Refresh)
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball FBGA
133.35 x 18.29 mm form factor
Lead-free Products are RoHS compliant


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