HYMP151F72CP4D3-C4 datasheet(3/32 Pages) HYNIX

Part #	HYMP151F72CP4D3-C4

Description	240pin Fully Buffered DDR2 SDRAM DIMMs

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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3 / 32 page

Rev 1.01 / Sep. 2008

3

1

240pin Fully Buffered DDR2 SDRAM DIMMs

Input/Output Functional Description

Pin Name

type

Polarity

Function Description

Count

SCK

Input

Positive

System clock input

1

SCK

Input

Negative

System clock input

1

PN[13:0]

Output

Positive

Primary Northbound Data

14

PN[13:0]

Output

Negative

Primary Northbound Data

14

PS[9:0]

Input

Positive

Primary Southbound Data

10

PS[9:0]

Input

Negative

Primary Southbound Data

10

SN[13:0]

Output

Positive

Secondary Northbound Data

14

SN[13:0]

Output

Negative

Secondary Northbound Data

14

SS[9:0]

Input

Positive

Secondary Southbound Data

10

SS[9:0]

Input

Negative

Secondary Southbound Data

10

SCL

Input

-

Serial Presence Detect (SPD) Clock Input

1

SDA

Input / Output

-

SPD Data Input / Output

1

SA[2:0]

Input

-

SPD Address inputs, also used to select the DIMM number in the AMB

3

VID[1:0]

Input

-

Voltage ID: These pins must be unconnected for DDR2-based Fully buff-

ered DIMMs

2

RESET

Input

Active Low

AMB reset signal

1

RFU

-

Reserved for Future Use

16

VCC

Supply

+1.5V

AMB Core Power and AMB channel Interface Power(1.5volt)

8

VDD

Supply

+1.8V

DRAM Power and AMB DRAM I/O Power

24

VTT

Supply

+0.9V

DRAM Address/Command/Clock Termination Power(VDD/2)

4

VDDSPD

Supply

+3.3V

SPD Power

1

VSS

Supply

Ground

80

DNU/M_Test

- / Analog

- / 0.9V

The DNU/M_Test pin provides an external connection on R/Cs A-D for

testing the margin of Vref which is produced by a voltage divider on the

module. It is not intended to be used in normal system operation and

must not be connected(DNU) in a system. This test pin may have other

features on future card designs and if it does, will be included in this

specification at that time.

1

Total

240

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