HYMP151F72CP4D5-Y5 datasheet(9/32 Pages) HYNIX

Part #	HYMP151F72CP4D5-Y5

Description	240pin Fully Buffered DDR2 SDRAM DIMMs

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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9 / 32 page

Rev 1.01 / Sep. 2008

9

1

240pin Fully Buffered DDR2 SDRAM DIMMs

FUNCTIONAL BLOCK DIAGRAM

4GB(512Mbx72) ECC FB-DIMM - 4 Rank

SN0-SN13

PN0-PN13

PS0-PS9

DQ0-DQ63

CB0-CB7

DQS0-DQS17

DQS0-DQS8

SCL

SA1-SA2

SDA

RESET

SCK/SCK

SN0-SN13

SS0-SS9

CKE0 -> CKE(D0-D17)

CKE1 -> CKE(D18-D35)

ODT0 -> ODT(D0-D17)

ODT1 -> ODT(D18-D26)

ODT2 -> ODT(D27-D35)

BA0-BA2 (all SDRAMs)

A0,A1-A3-A5-A7-A15(all SDRAMs)

A

Serial PD

WP A0 A1 A2

SA0 SA1 SA2

SCL

SDA

S2

S1

DQS5

DQS14

DQ40

DQ41

DQ42

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D5

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

DQ43

DQ44

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D14

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D23

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D32

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

S0

S3

DQS6

DQS15

DQ48

DQ49

DQ50

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D6

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

DQ51

DQ52

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D15

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D24

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D33

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

DQS7

DQS16

DQ56

DQ57

DQ58

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D7

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

DQ59

DQ60

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D16

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D25

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D34

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

DQS8

DQS17

DQ24

DQ25

DQ26

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D8

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

DQ27

DQ28

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D17

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D26

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

I/O 0

I/O 1

I/O 2

NU/

CS

DM/

D35

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

RDQS RDQS DQS DQS

M

B

A2,A6 (D0-D7, D8-D16, D‘8-D25, D27-D34)

A2_ECC, A6_ECC (D8, D17, D26, D35)

RAS (all SDRAMs)

CAS (all SDRAMs)

WE (all SDRAMs)

CK/CK (all SDRAMs)

SA0

D0–D17,AMB

VCC

SPD,AMB

VDDSPD

VTT

D0–D17

VREF

Terminators

VDD

VSS

AMB

D0–D17,SPD,AMB

All address/command/control/clock

VTT

Note:

1. DQ-to-I/O wiring may be changed within a byte.

2. There are two physical copies of each address/command/control/clock excluding

CKE0/1, ODT1/2, CS

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