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HMP125P7EFR8C-Y5 Datasheet(PDF) 9 Page - Hynix Semiconductor |
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HMP125P7EFR8C-Y5 Datasheet(HTML) 9 Page - Hynix Semiconductor |
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9 / 32 page  Rev. 0.3 / Oct. 2008 9 1 240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 4GB(512Mbx72) : HMP151P7EFR8C RDOT0 RCKE0 RS0 DQS0 DQS0 DQ7-0 DM0 DQS DQS DQ7-0 DM D0 DQS DQS DQ7-0 DM D9 RS1 DQS1 DQS1 DQ15-8 DM1 DQS DQS DQ7-0 DM D1 DQS DQS DQ7-0 DM D10 DQS2 DQS2 DQ23-16 DM2 DQS DQS DQ7-0 DM D2 DQS DQS DQ7-0 DM D11 DQS3 DQS3 DQ31-24 DM3 DQS DQS DQ7-0 DM D3 DQS DQS DQ7-0 DM D12 DQS4 DQS4 CB7-0 DM8 DQS DQS DQ7-0 DM D4 DQS DQS DQ7-0 DM D13 DQS4 DQS4 DQ39-32 DM4 DQS DQS DQ7-0 DM D5 DQS DQS DQ7-0 DM D14 DQS5 DQS5 DQ47-40 DM5 DQS DQS DQ7-0 DM D6 DQS DQS DQ7-0 DM D15 DQS6 DQS6 DQ55-48 DM6 DQS DQS DQ7-0 DM D7 DQS DQS DQ7-0 DM D16 DQS7 DQS7 DQ63-56 DM7 DQS DQS DQ7-0 DM D8 DQS DQS DQ7-0 DM D17 RDOT1 RCKE1 RS2 DQS DQS DQ7-0 DM D18 DQS DQS DQ7-0 DM D27 RS3 DQS DQS DQ7-0 DM D19 DQS DQS DQ7-0 DM D28 DQS DQS DQ7-0 DM D20 DQS DQS DQ7-0 DM D29 DQS DQS DQ7-0 DM D21 DQS DQS DQ7-0 DM D30 DQS DQS DQ7-0 DM D22 DQS DQS DQ7-0 DM D31 DQS DQS DQ7-0 DM D23 DQS DQS DQ7-0 DM D32 DQS DQS DQ7-0 DM D24 DQS DQS DQ7-0 DM D33 DQS DQS DQ7-0 DM D25 DQS DQS DQ7-0 DM D34 DQS DQS DQ7-0 DM D26 DQS DQS DQ7-0 DM D35 Serial PD WP A0 A1 A2 SA0 SA1 SA2 SCL SDA D0–D35 D0–D35 VREF SPD VDD/VDDQ VSS D0–D35 VDDSPD PCK7 -> CK: Register PCK7 -> CK: Register PCK0-PCK6, PCK8,PCK9 PCK0-PCK6, PCK8, PCK9 P L L CK0 CK0 RESET OE -> CK: SDRAMs D0-D35 -> CK: SDRAMs D0-D35 RS0 -> CS: SDRAMs D0-D8, RS2 -> CS: SDRAMs D18-D26 S0,S2* S1,S3* BA0-BA2*** A0-A15*** RAS CAS WE CKE0 CKE1 ODT1 ODT0 RESET** PCK7** PCK7** RS1 -> CS: SDRAMs D9-D17,RS3 -> CS: SDRAMs D27-D35 RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D35**** RA0-RA15 -> A0-A15: SDRAMs D0-D35**** RRAS -> RAS: SDRAMs D0-D35 RCAS -> CAS: SDRAMs D0-D35 RWE -> WE: SDRAMs D0-D35 RCKE0 -> CKE: SDRAMs D0-D17 RCKE1 -> CKE: SDRAMs D18-D35 RODT0 -> ODT0: SDRAMs D0-D8 RODT1 -> ODT1: SDRAMs D18-D26 1:2 R E G I S T E R RST Register A2 PAR_IN QERR Err_Out C1 C0 PPO VDD Vss Signals for Address and Command Register B2 PAR_IN QERR C1 C0 PPO VDD VDD Register A1 PAR_IN QERR C1 C0 PPO VDD Vss Register B1 PAR_IN QERR C1 C0 PPO VDD VDD Parity Function Register A1 and A2 share the a part of Addr/Cmd input signal set. Register B1 and B2 chare the rest part of Addr/Cmd input signal set. The resistors on Par_In, A13, A14. A15,BA2 and the signal line of Err_Out refer to the section: The egister Options for Unused Address inputs? * S0 (S2) connects to DCS0, S1 (S3) to DCS1 on a Register A. S1 (S3) connects to DCS and S0 (S2) connects to CSR on another pair of Register. * S2 and S3 have required upll up resistors (100k ohms), not indicated here. ** RESET, PCK7 and PCK7 connect to all Registers. Other signals connect to two of four Registers. *** A13-15, BA2 have the optional pull down resistors(100K ohms), which is not indicated here. **** For Raw Card N2, DQ stub resistor value is TBD. And for Raw Card N2, post register A14 and A15 are not connected to the SDRAMs. |
Similar Part No. - HMP125P7EFR8C-Y5 |
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Similar Description - HMP125P7EFR8C-Y5 |
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