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HMP151P7EFR4C-S5 Datasheet(PDF) 11 Page - Hynix Semiconductor |
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HMP151P7EFR4C-S5 Datasheet(HTML) 11 Page - Hynix Semiconductor |
11 / 26 page Rev. 0.2 / Sep. 2008 11 1 240pin Registered DDR2 SDRAM DIMMs INPUT DC LOGIC LEVEL INPUT AC LOGIC LEVEL AC INPUT TEST CONDITIONS Note: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF max to VIH(ac) min for rising edges and the range from VREF min to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions and VIH (ac) to VIL (ac) on the negative transitions. Parameter Symbol Min Max Unit Note dc Input logic HIGH VIH(DC) VREF + 0.125 VDDQ + 0.3 V dc Input logic LOW VIL(DC) -0.30 VREF - 0.125 V Parameter Symbol DDR2 400/533 DDR2 667/800 Unit Notes Min Max Min Max ac Input logic HIGH VIH(AC) VREF + 0.250 - VREF + 0.200 - V ac Input logic LOW VIL(AC) -VREF - 0.250 - VREF - 0.200 V Symbol Condition Value Units Notes VREF Input reference voltage 0.5 * VDDQ V1 VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1 SLEW Input signal minimum slew rate 1.0 V/ns 2, 3 VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS < Figure: AC Input Test Signal Waveform > VSWING(MAX) ∆TR ∆TF Start of Falling Edge Input Timing Start of Rising Edge Input Timing VREF - VIL(ac) max ∆TF Falling Slew = Rising Slew = VIH(ac) min - VREF ∆TR |
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