Rev. 0.2 / December 2008

11

3. Functional Block Diagram

3.1 1GB, 128Mx72 Module(1Rank of x8)

CB[7:0]

DQS8_t

DQS8_c

DM8/DQS17_t

DQS17_c

Vtt

DQ[31:24]

DQS3_t

DQS3_c

DM3/DQS12_t

DQS12_c

DQ[23:16]

DQS2_t

DQS2_c

DM2/DQS11_t

DQS11_c

DQ[15:8]

DQS1_t

DQS1_c

DM1/DQS10_t

DQS10_c

DQ[7:0]

DQS0_t

DQS0_c

DM0/DQS9_t

DQS9_c

DQS_t

DQS_c

TDQS_t

TDQS_c

D8

DQ [7:0]

ZQ

DQS_t

DQS_c

TDQS_t

TDQS_c

D3

DQ [7:0]

ZQ

DQS_t

DQS_c

TDQS_t

TDQS_c

D2

DQ [7:0]

ZQ

DQS_t

DQS_c

TDQS_t

TDQS_c

D1

DQ [7:0]

ZQ

DQS_t

DQS_c

TDQS_t

TDQS_c

D0

DQ [7:0]

ZQ

DQ[39:32]

DQS4_t

DQS4_c

DM4/DQS13_t

DQS13_c

Vtt

DQ[47:40]

DQS5_t

DQS5_c

DM5/DQS14_t

DQS14_c

DQ[55:48]

DQS6_t

DQS6_c

DM6/DQS15-t

DQS15_c

DQ[63:56]

DQS7_t

DQS7_c

DM7/DQS16_t

DQS16_c

DQS_t

DQS_c

TDQS_t

TDQS_c

D4

DQ [7:0]

ZQ

DQS_t

DQS_c

TDQS_t

TDQS_c

D5

DQ [7:0]

ZQ

DQS_t

DQS_c

TDQS_t

TDQS_c

D6

DQ [7:0]

ZQ

DQS_t

DQS_c

TDQS_t

TDQS_c

D7

DQ [7:0]

ZQ

S0_n

S1_n

BA[N:0]

A[N:0]

RAS_n

CAS_n

WE_n

CKE0

ODT0

CK0_t

CK0_c

PAR_IN

RS0A_n → CS0_n: SDRAMs D[3:0], D8

RS0BCK_n → CS0_n: SDRAMs D[7:4]

RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D8

RRASB_n → RAS_n: SDRAMs D[7:4]

RBA[N:0]B → BA[N:0]: SDRAMs D[7:4]

RA[N:0]B → A[N:0]: SDRAMs D[7:4]

RA[N:0]A → A[N:0]: SDRAMs D[3:0], D8

RRASA_n → RAS_n: SDRAMs D[3:0], D8

RCASB_n → CAS_n: SDRAMs D[7:4]

RCASA_n → CAS_n: SDRAMs D[3:0], D8

RWEB_n → WE_n: SDRAMs D[7:4]

RWEA_n → WE_n: SDRAMs D[3:0], D8

RCKE0B → CKE0: SDRAMs D[7:4]

RCKE0A → CKE0: SDRAMs D[3:0], D8

RODT0B → ODT0: SDRAMs D[7:4]

RODT0A → ODT0: SDRAMs D[3:0], D8

PCK0B_t → CK_t: SDRAMs D[7:4]

PCK0A_t → CK_t: SDRAMs D[3:0], D8

PCK0B_c → CK_c: SDRAMs D[7:4]

PCK0A_c → CK_c: SDRAMs D[3:0], D8

Err_Out_n

OERR_n

RESET_n

RST_n

RST_n: SDRAMs D[8:0]

S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 120...330Ω resistor to ground

1:

2

R

E

G

I

S

T

E

R

/

P

D0–D8

D0–D8

VREFDQ

SPD

VREFCA

D0–D8

D0–D8

Note:

1.DQ-to-I/O wiring may be changed within byte.

appropriate wiring diagram.

VDDSPD

EVENT

SCL

SDA

SA0

SPD with

Integrated

TS

SA1

SA2

VSS

VDDSPD

EVENT

SCL

SDA

SA0

SA1

SA2

VSS

Plan to use SPD with Integrated TS of Class B and

might be changed on customer’s requests. For more

details of SPD and Thermal sensor, please contact

local Hynix sales representative

120Ω

± 1%

CK1_t

CK1_c

120Ω

± 1%

L

L