HMT351V7AMP4C-G7 datasheet(6/25 Pages) HYNIX

Part #	HMT351V7AMP4C-G7

Description	240pin DDR3 SDRAM VLP Registered DIMM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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6 / 25 page

Rev. 0.2 / December 2008

6

2. Pin Architecture

2.1 Pin Definition

Pin Name

Description

Num

-ber

Name

Description

Num

-ber

A0–A9,A11

A13-A15

Address Inputs

14

A10/AP

Address Input/Autoprecharge

1

BA0–BA2

SDRAM Bank Addresses

3

A12/BC

Address Input/Autoprecharge

1

RAS

Row Address Strobe

1

SCL

Serial Presence Detect (SPD) Clock Input

1

CAS

Column Address Strobe

1

SDA

SPD Data Input/Output

1

WE

Write Enable

1

SA0–SA2 SPD Address Inputs

3

S0–S3Chip Selects

4

Par_in

Parity Bit For The Address and Control

Bus

1

CKE0–CKE1

Clock Enables

2

ERR_OUT Parity Error Found on the Address and

Control Bus

1

ODT0–ODT1

On-die termination Inputs

2

EVENT

Reserved for Optional Hardware

temperature Sensing

1

DQ0–DQ63

Data Input/Output

64

TEST

Memory Bus Test Tool (Not Connected

and Not Usable on DIMMs)

1

CB0–CB7

Data Check Bits Input/Output

8

RESET

Register and SDRAM control pin

1

DQS0–DQS8

Data Strobes

9

VDD

Power Supply

22

DQS0–DQS8

Data Strobes, Negative Line

9

VSS

Ground

59

DM0–DM8

DQS9-DQS17

TDQS9-TDQS17

Data Masks

Data Strobes

Termination Data Strobes

9

VREFDQ

Reference Voltage for DQ

1

VREFCA

Reference Voltage for CA

1

VTT

Termination Voltage

4

DQS9–DQS17

TDQS9–TDQS17

Data Strobes, Negative Line

Termination Data Strobes

9

VDDSPD

SPD Power

1

CK1

Clock Input, positive line

1

CK0

Clock Input, positive line

1

CK1

Clock Input, negative line

1

CK0

Clock Input, positive Line

1

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