Rev. 0.1 / Jan. 2009

8

1

240pin Registered DDR2 SDRAM DIMMs

INPUT DC LOGIC LEVEL

INPUT AC LOGIC LEVEL

AC INPUT TEST CONDITIONS

Note:

1.

2.

3.

AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to

VIL(ac) on the negative transitions.

Parameter

Symbol

Min

Max

Unit

Note

dc Input logic HIGH

V

dc Input logic LOW

-0.30

V

Parameter

Symbol

DDR2 667/800

Unit

Notes

Min

Max

ac Input logic HIGH

-

V

ac Input logic LOW

V

Symbol

Condition

Value

Units

Notes

Input reference voltage

V1

Input signal maximum peak to peak swing

1.0

V

1

SLEW

Input signal minimum slew rate

1.0

V/ns

2, 3

< Figure: AC Input Test Signal Waveform >

Start of Falling Edge Input Timing

Start of Rising Edge Input Timing

Falling Slew =

Rising Slew =