HMP525F7FFP4C-C4 datasheet(8/26 Pages) HYNIX

Part #	HMP525F7FFP4C-C4

Description	240pin Fully Buffered DDR2 SDRAM DIMMs based on 512 Mb F-ver.

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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8 / 26 page

Rev 1.2 / Feb. 2009

8

1

240pin Fully Buffered DDR2 SDRAM DIMMs

Architecture

Advanced Memory Buffer Pin Description

Pin Name

Pin Description

Count

FB-DIMM Channel Signals

99

SCK

System Clock Input, positive line

1

SCK

System Clock Input, negative line

1

PN[13:0]

Primary Northbound Data, positive lines

14

PN[13:0]

Primary Northbound Data, negative lines

14

PS[9:0]

Primary Southbound Data, positive lines

10

PS[9:0]

Primary Southbound Data, negative lines

10

SN[13:0]

Secondary Northbound Data, positive lines

14

SN[13:0]

Secondary Northbound Data, negative lines

14

SS[9:0]

Secondary Southbound Data, positive lines

10

SS[9:0]

Secondary Southbound Data, negative lines

10

FBDRES

To an external precision calibration resistor connected to Vcc

1

DDR2 Interface Signals

175

DQS[8:0]

Data Strobes, positive lines

9

DQS[8:0]

Data Strobes, negative lines

9

DQS[17:9]/DM[8:0]

Data Strobes(x4 DRAM only), positive lines. These signals are driven low to x8

DRAM on writes.

9

DQS[17:9]

Data Strobes(x4 DRAM only), negative lines

9

DQ[63:0]

Data

64

CB[7:0]

Checkbits

8

A[15:0]A,A[15:0]B

Addresses. A10 is part of the pre-charge command

32

BA[2:0]A,BA[2:0]B

Bank Addresses

6

RASA,RASB

Part of command, with CAS, WE and CS[1:0]

2

CASA,CASB

Part of command, with RAS, WE and CS[1:0]

2

WEA,WEB

Part of command, with RAS, WE and CS[1:0]

2

ODTA,ODTB

On-die Termination Enable

2

CKE[1:0]A,CKE[1:0]B

Clock Enable(one per rank)

4

CS[1:0]A,CS[1:0]B

Chip Select(One per rank)

4

CLK[3:0]

CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs.

CLK[3:2] should be output disabled when not in use.

4

CLK[3:0]

Negative lines for CLK[3:0]

4

DDRC_C14

DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18

1

DDRC_B18

DDR Compensation: Resistor connected to common return pin DDRC_C14

1

DDRC_C18

DDR Compensation: Resistor connected to common return pin DDRC_C14

1

DDRC_B12

DDR Compensation: Resistor connected to VSS

1

DDRC_C12

DDR Compensation: Resistor connected to VDD

1

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