HYMD132G725B(L)4-M/K/H/L

Rev. 0.3/May. 02

11

Note :

1.

This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2.

Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

3.

For command/address input slew rate >=1.0V/ns

4.

For command/address input slew rate >=0.5V/ns and <1.0V/ns

This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

5.

CK, /CK slew rates are >=1.0V/ns

6.

These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by

design or tester correlation.

7.

Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.

8.

Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

9.

Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of

tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to

n-channel variation of the output drivers.

11

Input Setup / Hold Slew-rate Derating Table.

12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF

+/-310mV for a duration of up to 2ns.

13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS

slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns

and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.

14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotonic.

Input Setup / Hold Slew-rate

Delta tIS

Delta tIH

V/ns

ps

ps

0.5

0

0

0.4

+50

0

0.3

+100

0

Input Setup / Hold Slew-rate

Delta tDS

Delta tDH

V/ns

ps

ps

0.5

0

0

0.4

+75

+75

0.3

+150

+150

I/O Input Level

Delta tDS

Delta tDH

mV

ps

ps

+280

+50

+50

(1/SlewRate1)-(1/SlewRate2)

Delta tDS

Delta tDH

ns/V

ps

ps

00

0

+/-0.25

+50

+50

+/- 0.5

+100

+100