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HYMD216M726AL6-K Datasheet(PDF) 8 Page - Hynix Semiconductor

Part # HYMD216M726AL6-K
Description  Unbuffered DDR SO-DIMM
Download  19 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HYMD216M726AL6-K Datasheet(HTML) 8 Page - Hynix Semiconductor

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HYMD216M726A(L)6-J/M/K/H/L
Rev. 0.3/Oct. 02
8
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-J
-M
-K
-H
-L
Operating Current
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs
changing twice per clock cycle; address and
control inputs changing once per clock cycle
525
525
475
475
450
mA
Operating Current
IDD1
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per
clock cycle
750
750
650
650
600
mA
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
100
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE= High; address and control inputs
changing once per clock cycle. VIN=VREF for
DQ, DQS and DM
250
250
200
200
175
mA
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode;
CKE=Low, tCK=tCK(min)
125
mA
Idle Quiet Standby
Current
IDD2Q
/CS>=Vih(min); All banks idle;
CKE>=Vih(min); Addresses and other control
inputs stable, Vin=Vref for DQ, DQS and DM
TBD
mA
Active Standby
Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
300
300
250
250
250
mA
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
1450
1450
1250
1250
950
mA
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock
cycle
1450
1450
1250
1250
950
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at
100Mhz, 10*tCK for DDR266A & DDR266B at
133Mhz; distributed refresh
1150
1150
1050
1050
975
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK =tCK(min)
Normal
15
mA
Low Power
7.5
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
1675
1675
1625
1625
1450
mA
Random Read Current
IDD7A
4banks active read with activate every 20ns,
AP(Auto Precharge) read every 20ns, BL=4,
tRCD=3, IOUT=0 mA, 100% DQ, DM and
DQS inputs changing twice per clock cycle;
100% addresses changing once per clock
cycle
TBD
mA


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