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HYMD232M726A8-L Datasheet(PDF) 7 Page - Hynix Semiconductor |
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HYMD232M726A8-L Datasheet(HTML) 7 Page - Hynix Semiconductor |
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7 / 17 page  HYMD232M726A(L)8-J/M/K/H/L Rev. 0.2/Oct. 02 7 DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Symbol Test Condition Speed Unit Note -J -M -K -H -L Operating Current IDD0 One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle ; address and control inputs changing once per clock cycle 945 945 855 855 810 mA 1 Operating Current IDD1 One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle 1350 1350 1170 1170 1080 mA 1 Precharge Power Down Standby Current IDD2P All banks idle; Power down - mode; CKE=Low, tCK=tCK(min) 180 mA 1 Idle Standby Current IDD2F /CS=High, All banks idle; tCK=tCK(min); CKE= High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM 450 450 360 360 315 mA 1 Active Power Down Standby Current IDD3P One bank active; Power down mode; CKE=Low, tCK=tCK(min) 225 mA 1 Idle Quiet Standby Current IDD2Q /CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref for DQ, DQS and DM TBD mA Active Standby Current IDD3N /CS=HIGH; CKE=HIGH; One bank; Active- Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle 540 540 450 450 450 mA 1 Operating Current IDD4R Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA 2610 2610 2250 2250 1710 mA 1 Operating Current IDD4W Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle 2610 2610 2250 2250 1710 1 Auto Refresh Current IDD5 tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh 2070 2070 1890 1890 1755 1 Self Refresh Current IDD6 CKE=<0.2V; External clock on; tCK =tCK(min) Normal 27 mA 1 Low Power 13.5 mA 1 Operating Current - Four Bank Operation IDD7 Four bank interleaving with BL=4 Refer to the following page for detailed test condition 2835 2835 2745 2745 2520 mA 1 Random Read Current IDD7A 4banks active read with activate every 20ns, AP(Auto Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA, 100% DQ, DM and DQS inputs changing twice per clock cycle; 100% addresses changing once per clock cycle TBD mA |
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Similar Description - HYMD232M726A8-L |
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